Spi Slave Register - Motorola DragonBall MC68328 User Manual

9.4.1 SPI Slave Register

This register controls the SPI operation and reports its status. The lower byte is the input
data received from an external source.
15 14 13 12
SPIS DATA
IRQEN ENPOL
IRQ RDY
Address: $(FF)FFF700:
SPISIRQ- SPIS IRQ
This interrupt-flag bit is asserted at the end of an 8-bit transfer. The data buffer should be
read before the completion of another 8-bit transfer. This flag is automatically cleared after
reading.
0 = No interrupt posted
1 = Interrupt posted
IRQEN- SPIS_IRQ Enable
This bit enables the SPIS_IRQ interrupt and is cleared on reset.
0 = Interrupt disabled
1 = Interrupt enabled
ENPOL- SPSEN Polarity Control
This bit controls the polarity of the SPSEN signal and is initially set to 0.
0= SPSEN is active-low
1= SPSEN is active-high
DATARDY- Data Ready
This flag indicates that the data buffer contains updated data. The DATARDY flag is au-
tomatically cleared after the data is read.
0=Buffer is empty
1=Buffer has data
OVRWR- Overwrite
This bit indicates that the data buffer was overwritten. An interrupt is posted when an over-
write occurs. The OVRWR flag is automatically cleared after the data is read.
0=Data buffer is intact
1=Data buffer has been overwritten, data stream is corrupted
PHA
This bit sets the phase relationship between SPSCLK and SPSRxD. Refer to Figure 9-2.
0 = Phase 0 (normal); data is captured on the leading edge of SPSCLK
1 = Phase 1; data is captured on the trailing edge of SPSCLK
MOTOROLA MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
11 10 9 8
OVRWR PHA POL SPISEN
Figure 9-3. SPI Slave Register
7 6 5 4
DATA
SPI-Slave
3 2 1 0
Reset Value: $0000
9-3