Uart Control Register - Motorola DragonBall MC68328 User Manual

interrupt sources. While the UART EN bit is low, the master clock to all UART blocks is dis-
abled, reducing power consumption to a minimum.

8.2.5 UART Control Register

This register controls the overall UART operation. This register resets to $0000.
15 14 13 12
UART RX TX RX CLK
ENABLE ENABLE ENABLE CONT
ADDRESS: $(FF)FFF900
UART ENABLE
This bit enables the UART. While this bit is low, the UART is disabled and in low-power
mode. While this bit is high, the UART is active. This bit resets to 0.
0 = UART disabled
1 = UART enabled
When the UART is first enabled after cold reset, before enabling
interrupts, set the UART ENABLE and RX ENABLE bits and per-
form a word-read operation on the receiver register to initialize
the FIFO and character-status bits.
RX ENABLE
This bit enables the receiver block. While this bit is low, the receiver is disabled and the
receive FIFO is flushed. This bit resets to 0.
0 = Receiver disabled and receive FIFO flushed
1 = Receiver enabled
TX ENABLE
This bit enables the transmitter block. While this bit is low, the transmitter is disabled and
the transmit FIFO is flushed. This bit resets to 0.
0 = Transmitter disabled and transmit FIFO flushed
1 = Transmitter enabled
RX CLK CONT
This bit controls the receiver operating mode of the receiver. While low, the receiver is in
16x mode where it synchronizes to the incoming data stream and samples at the per-
ceived center of each bit period. While high, the receiver is in 1x mode where it samples
the data stream on each rising edge of the bit clock. This bit resets to 0.
0 = 16x clock mode
1 = 1x clock mode
MOTOROLA MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
11 10 9
PARITY ODD STOP
EN EVEN BITS
Figure 8-2. UART Control Register
Receiver Clock Control
8 7 6 5
GPIO CTS
RX FULL
8/7 DELTA DELTA
ENABLE
ENABLE ENABLE
NOTE
4 3 2 1
RX TX
RX RDY TX HALF
HALF EMPTY
ENABLE ENABLE
ENABLE ENABLE
Reset Value: $0000
UART
0
TX
AVAIL
ENABLE
8-5