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Timing Of Host Interface (Dma Single) - Toshiba SD-M1212 - DVD-ROM Drive - IDE Specifications

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6.2.3.Timing of Host Interface (DMA Single)

Figure 9 shows the Host Interface DMA single word Timings
DMARQ
DMACK-*1
DIOR-/DIOW-*1
Read
DD0-15
Write
DD0-15
*1: In all timing diagrams, the low line indicator negated, and the upper line
indicators asserted.
Single word DMA
timing parameters min(ns) max(ns)
Cycle time
t0
DMACK to DMREQ delay
tC
DIOR-/DIOW-
tD
DIOR- data access
tE
DIOR- data hold
tF
DIOW- data setup
tG
DIOW- data hold
tH
DMACK to DIOR-/DIOW- setup
tI
DIOR-/DIOW- to DMACK hold
tJ
DIOR- setup
tS
Figure 9 Host Interface Timing (DMA Single)
tC
tI
tE
16-bit
15/28
t0
tJ
tD
tF
tS
tG
tH
Min time
(ns)
240
120
5
35
20
0
0
tD - tE
Max time
(ns)
80
60
SD-M1212 Rev.1.0

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