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S1F76600 Series
TYPICAL APPLICATIONS
Parallel Connection
Connecting two or more chips in parallel reduces the
output impedance by 1/n, where n is the number of de-
vices used.
V
= –5 V
I
1M
Serial Connection
Connecting two or more chips in series obtains a higher
output voltage than can be obtained using a parallel
V
= –5 V
I
1M
Potential levels
V
DD
V
(–5 V)
I
1–8
V
= 0 V
DD
5 V
1
8
+
2
7
3
6
+
4
5
V
= 0 V
DD
5 V
1
8
2
7
3
6
4
5
(0 V)
V
DD
V
'
V
(–10 V)
I
O
Primary stage
1
C2
10 F
2
1M
3
C1
10 F
4
connection, however, this also raises the output imped-
ance.
V
' = V
= –5
DD
I
1
+
C2
10 F
2
1M
3
C1
+
10 F
4
V
= –10 V = V
'
O
I
'
V
' (–15 V)
O
Secondary stage
EPSON
8
7
6
C1
+
10 F
5
V
= –10 V
O
8
+
C2
10 F
7
6
C1
+
10 F
5
V
' = –15 V
O
S1F70000 Series
Technical Manual
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