Adc - HP 8560A Service Manual

See function block F of A3 Interface Assembly Schematic Diagram (sheet 2 of 6).
1. Press (=I) on the HP 8560A and set the controls as follows:
SPAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 Hz
SWEEP TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..~OS
DETECTOR MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAMPLE
2. Check that HSTART_SRC (U504 pin 4) goes TTL high, causing HHOLD (U506 pin 16) to
go high 15 /.JS later.
3. Check that HSTART_ADC (U506 pin 15) g oes TTL high 19 ps after HSTART_SRC goes
high.
4. HHOLD should stay TTL high for approximately 18 ps, and HSTART_ADC should stay
high for approximately 31 ps.
5. Check that LCMPLT (U504 pin 15) goes TTL low 12 ps after HSTART_ADC goes high
(12 bits at 1 ps per bit). LCMPLT indicates that the successive approximation register
(SAR) has completed the ADC conversion.
6. Check that LDONE (U506 pin 19) goes TTL low approximately 2 ps after LCMPLT goes
low.

ADC

See function block A of A3 Interface Assembly Schematic Diagram (sheet 2 of 6).
The successive approximation register (SAR) consists of A3U513. Upon the occurrence of
HSTART_ADC, the SAR successively toggles bits from high to low starting with the most
significant bit. The digital result is then converted to an analog current in DAC U518 and
compared with the SAMPLED VIDEO. If the DAC current is too high, the output of U512
will be high, telling the SAR that the "guess" was high and that the bit just toggled should be
set low. It then moves on to the next most significant bit until all 12 bits have been "guessed"
at. Each "guess" takes 1 ps (one cycle of HBADC-CLKO), or 12 ps to complete a conversion.
When the conversion is completed, the SAR sets LCMPLT low. The bits are written to the
data bus by buffers U514 and U516.
1. Set the HP 8560A controls as follows:
C E N T E R F R E Q
SPAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 Hz
SWEEP TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60s
DETECTOR MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAMPLE
2. Trigger an oscilloscope on HSTART_ADC (U506 pin 15) and monitor the outputs Ql
through Qll of the SAR. With the exception of Qll, each bit should start high and be
switched low. It will either stay low or return to a high state 1 ps later, depending on the
comparison at U512.
3. If the Q outputs do not exhibit this bit pattern, and the ADC ASM checks are working
properly, replace U513. If the output of comparator U512 does not toggle back and forth
during a conversion, replace either U512 or CR502.
7-24 ADC/lnterface Section
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..300MHz