Pioneer MJ-D707 Service Manual page 51

PD5450A (IC104: CORE MAIN UNIT ASSY)
Mechanism Control m-com.
Pin Assignment (Top view)
Block Diagram
I/O PORT
Port P0
Internal Peripheral
Functions
TIMER
Timer TA0 (16bits)
Timer TA1 (16bits)
Timer TA2 (16bits)
Timer TA3 (16bits)
Timer TA4 (16bits)
Timer TB0 (16bits)
Timer TB1 (16bits)
Timer TB2 (16bits)
Monitoring timer
(16 bits)
DMAC (2 channels)
D/A Converter
(8bits 2 channels)
8 8 8
Port P1 Port P2
A/D Converter
(10bits 8 channels)
(expansion to 10 channels possible)
UART/clock-synchronized SI/O
(8bits 2 channels)
CHC operation circuit
(CCITT method)
16
(formation polynomial: X + X
16 bits CPU CORE
Register
R0L
R0H
R0L
R0H
R1H R1L
R1H R1L
R2
R2
R3
R3
A0
A0
A1
A1
FB
FB
SB
8 8 8
Port P3 Port P4 Port P5
System clock generation
XIN – XOUT
XCIN – XCOUT
12 5
+ X + 1)
MEMORY
Stack Pointer
ROM
ISP
USP
Vector Table
RAM
INTB
10k bite
Analog Multiplier
MJ-D707, MJ-17D
8
Port P6
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