Acer AR320 F2 Service Manual page 49

Acer ar320 f2 server service guide
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P-State Coordination
C1E Support
CPU C3 Report
CPU C6 Report
Package C State Limit
Hardware Prefetcher
Adjacent Cache Line
Prefetch
CPU Speed
EMT64
Core Count
CPU Stepping
Microcode Revision
Intel HT Technology
In HW_ALL mode, the processor hardware is
responsible for coordinating the P-state among logical
processors dependencies. The OS is responsible for
keeping the P-state request up to date on all logical
processors.
In SW_ALL mode, the OS Power Manager is
responsible for coordinating the P-state among logical
processors with dependencies and must initiate the
transition on all of those Logical Processors.
In SW_ANY mode, the OS Power Manager is
responsible for coordinating the P-state among logical
processors with dependencies and may initiate the
transition on any of those Logical Processors.
Select whether to enable the C1 Enhanced mode for the
processor. If enabled, all logical processors in a physical
processor will run in a C1 state.
Enable/Disable C3 Report.
Enable/Disable C6 Report.
Configure state for the C-State package limit.
Select whether to enable the speculative prefetch unit of
the processor
When enabled, cache lines are fetched in pairs. When
disabled, only the required cache line is fetched.
The processor speed is the speed at which a
microprocessor executes instructions. Clock speeds are
expressed in megahertz (MHz), with
1 MHz being equal to 1 million cycles per second. The
faster the clock, the more instructions the CPU can
execute per second.
Display Processor EMT64 support status
Display Processor core count information.
Display processor stepping information.
Display Microcode Revision.
Display Intel Hyper Threading Technology function
support information.
45
HW_ALL
SW_ALL
SW_ANY
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
C0
C1
C6
C7
No Limit
Enabled
Disabled
Enabled
Disabled

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