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Mitsubishi Electric 740 Series User Manual
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Mitsubishi Electric 740 Series User Manual

Mitsubishi Electric 740 Series User Manual

8-bit single-chip microcomputer
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MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 740 SERIES
7540
G r o u p
User's Manual
http://www.infomicom.maec.co.jp/indexe.htm
Before using this material, please visit the above website to confirm that this is the most
current document available.
Rev. 1.0
Revision date: Sep, 17 2002

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  • Page 1 MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 740 SERIES 7540 G r o u p User’s Manual http://www.infomicom.maec.co.jp/indexe.htm Before using this material, please visit the above website to confirm that this is the most current document available. Rev. 1.0 Revision date: Sep, 17 2002...
  • Page 2 The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or repro- duce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be im- ported into a country other than the approved destination.
  • Page 3 REVISION HISTORY 7540 GROUP USER’S MANUAL Rev. Date Description Page Summary 09/17/02 First Edition (1/2)
  • Page 4 Preface This user’s manual describes Mitsubishi’s CMOS 8- bit microcomputers 7540 Group. After reading this manual, the user should have a through knowledge of the functions and features of the 7540 Group, and should be able to fully utilize the product. The manual starts with specifications and ends with application examples.
  • Page 5 BEFORE USING THIS MANUAL This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. Chapter 3 also includes necessary information for systems development. You must refer to that chapter. 1.
  • Page 6 Table of contents Table of contents CHAPTER 1 HARDWARE DESCRIPTION ..........................1-2 FEATURES ............................1-2 APPLICATION ..........................1-2 PIN CONFIGURATION ........................1-3 FUNCTIONAL BLOCK ........................1-5 PIN DESCRIPTION ........................1-8 GROUP EXPANSION ........................1-9 FUNCTIONAL DESCRIPTION ....................1-11 Central Processing Unit (CPU) .................... 1-11 Memory ............................
  • Page 7 Table of contents CHAPTER 2 APPLICATION 2.1 I/O port ............................. 2-2 2.1.1 Memory map ........................2-2 2.1.2 Relevant registers ......................2-3 2.1.3 Application example of key-on wake up (1) ............... 2-7 2.1.4 Application example of key-on wake up (2) ............... 2-9 2.1.5 Handling of unused pins .....................
  • Page 8 Table of contents 2.9 Oscillation control ......................2-135 2.9.1 Memory map ....................... 2-135 2.9.2 Relevant registers ...................... 2-135 2.9.3 Application example of ring oscillator ..............2-137 2.9.4 Oscillation stop detection circuit ................2-139 2.9.5 State transition ......................2-142 2.9.6 Notes on oscillation stop detection circuit .............. 2-145 CHAPTER 3 APPENDIX 3.1 Electrical characteristics .....................
  • Page 9 List of figures List of figures CHAPTER 1 HARDWARE Fig. 1 Pin configuration (32P6U-A type) ..................1-3 Fig. 2 Pin configuration (36P2R-A type) ..................1-3 Fig. 3 Pin configuration (32P4B-A type) ..................1-4 Fig. 4 Pin configuration (42S1M type) ..................1-4 Fig.
  • Page 10 List of figures Fig. 49 Processing of X and X pins at ring oscillator operation ........1-45 Fig. 50 Structure of MISRG ......................1-46 Fig. 51 Block diagram of internal clock generating circuit (for ceramic resonator) ... 1-47 Fig. 52 Block diagram of internal clock generating circuit (for RC oscillation) ....1-47 Fig.
  • Page 11 List of figures Fig. 2.3.1 Memory map of registers relevant to timer 1 ............2-36 Fig. 2.3.2 Structure of Prescaler 1 .................... 2-36 Fig. 2.3.3 Structure of Timer 1 ....................2-37 Fig. 2.3.4 Structure of MISRG ....................2-37 Fig. 2.3.5 Structure of Interrupt request register 2 ..............2-38 Fig.
  • Page 12 List of figures Fig. 2.5.21 Method of measuring water flow rate ..............2-75 Fig. 2.5.22 Example of control procedure ................2-76 Fig. 2.5.23 Timing diagram of programmable waveform generation mode ......2-79 Fig. 2.5.24 Setting method for programmable waveform generation mode (1) ....2-80 Fig.
  • Page 13 List of figures Fig. 2.7.11 Control procedure of transmission side .............. 2-126 Fig. 2.7.12 Control procedure of reception side ..............2-127 Fig. 2.8.1 Memory map of registers relevant to A-D converter .......... 2-129 Fig. 2.8.2 Structure of A-D control register ................2-129 Fig.
  • Page 14 List of figures Fig. 3.2.16 V characteristics (I/O port (CMOS): Mask ROM version) ......3-37 Fig. 3.2.17 V characteristics (I/O port (TTL): Mask ROM version) ......3-37 Fig. 3.2.18 V characteristics (RESET pin: Mask ROM version) ......... 3-38 Fig. 3.2.19 V characteristics (X pin: Mask ROM version) .........
  • Page 15 List of figures Fig. 3.2.58 Ta-I characteristics (When system is operating by ring oscillator, at WIT instruction execution, Ceramic oscillation stop: One Time PROM version) ........3-57 Fig. 3.2.59 V characteristics (I/O port (CMOS): One Time PROM version) ..... 3-58 Fig.
  • Page 16 List of figures Fig. 3.4.1 Selection of packages ....................3-92 Fig. 3.4.2 Wiring for the RESET pin ..................3-92 Fig. 3.4.3 Wiring for clock I/O pins ................... 3-93 Fig. 3.4.4 Wiring for CNV pin ....................3-93 Fig. 3.4.5 Wiring for the V pin of the One Time PROM .............
  • Page 17 List of figures Fig. 3.10.1 32P6U-A package pin configuration ..............3-135 Fig. 3.10.2 36P2R-A package pin configuration ..............3-136 Fig. 3.10.3 32P4B package pin configuration ................ 3-137 Fig. 3.10.4 42S1M package pin configuration ................ 3-138 Fig. 3.11.1 Memory map of 7540 Group and 7531 Group ..........3-140 Fig.
  • Page 18 List of tables List of tables CHAPTER 1 HARDWARE Table 1 Pin description ......................... 1-8 Table 2 List of supported products ................... 1-10 Table 3 Push and pop instructions of accumulator or processor status register ....1-12 Table 4 Set and clear instructions of each bit of processor status register ....... 1-13 Table 5 I/O port function table ....................
  • Page 19 Table 3.1.28 A-D Converter characteristics ................3-27 Table 3.1.29 Timing requirements (1) ..................3-28 Table 3.1.30 Timing requirements (2) ..................3-28 Table 3.1.31 Switching characteristics (1) ................3-29 Table 3.1.32 Switching characteristics (2) ................3-29 Table 3.3.1 Programming adapters ................... 3-91 Table 3.3.2 PROM programmer address setting ..............
  • Page 20 C H A P T E R 1 HARDWARE DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION FUNCTIONAL BLOCK PIN DESCRIPTION GROUP EXPANSION FUNCTIONAL DESCRIPTION NOTES ON PROGRAMMING NOTES ON USE DATA REQUIRED FOR MASK ORDERS ROM PROGRAMMING METHOD FUNCTIONAL DESCRIPTION SUPPLEMENT...
  • Page 21 HARDWARE DESCRIPTION/FEATURES/APPLICATION DESCRIPTION APPLICATION The 7540 Group is the 8-bit microcomputer based on the 740 fam- Office automation equipment, factory automation equipment, ily core technology. home electric appliances, consumer electronics, car, etc. The 7540 Group has a serial I/O, 8-bit timers, a 16-bit timer, and Notes 1: Serial I/O2 can be used in the following cases;...
  • Page 22 HARDWARE PIN CONFIGURATION PIN CONFIGURATION (TOP VIEW) (LED M37540Mx-XXXGP (LED M37540MxT-XXXGP (LED M37540MxV-XXXGP CLK1 CLK2 (LED M37540ExGP (LED RDY1 DATA2 M37540E8T-XXXGP /CNTR M37540E8V-XXXGP Package type: 32P6U-A Fig. 1 Pin configuration (32P6U-A type) CLK1 CLK2 RDY1 DATA2 /CNTR /CNTR /INT (LED )/INT (LED RESET...
  • Page 23 HARDWARE PIN CONFIGURATION CLK1 CLK2 RDY1 DATA2 /CNTR /CNTR /INT RESET (LED (LED (LED (LED (LED Package type: 32P4B Fig. 3 Pin configuration (32P4B-A type) /CNTR RDY1 DATA2 CLK1 CLK2 /CNTR /INT (LED )/INT RESET (LED (LED (LED (LED (LED (LED Outline 42S1M Fig.
  • Page 24 HARDWARE FUNCTIONAL BLOCK FUNCTIONAL BLOCK Fig. 5 Functional block diagram (32P6U package) 7540 Group User’s Manual...
  • Page 25 HARDWARE FUNCTIONAL BLOCK Fig. 6 Functional block diagram (36P2R package) 7540 Group User’s Manual...
  • Page 26 HARDWARE FUNCTIONAL BLOCK Fig. 7 Functional block diagram (32P4B package) 7540 Group User’s Manual...
  • Page 27 HARDWARE PIN DESCRIPTION PIN DESCRIPTION Table 1 Pin description Name Function Function expect a port function Vcc, Vss Power source •Apply voltage of 2.2 to 5.5 V to Vcc, and 0 V to Vss. (Note 1) Analog reference •Reference voltage input pin for A-D converter voltage CNVss CNVss...
  • Page 28 HARDWARE GROUP EXPANSION GROUP EXPANSION Memory size Mitsubishi plans to expand the 7540 group as follow: ROM/PROM size ..........8 K to 32 K bytes RAM size .............. 384 to 768 bytes Memory type Support for Mask ROM version, One Time PROM version, and Package Emulator MCU .
  • Page 29 HARDWARE GROUP EXPANSION Currently supported products are listed below. Table 2 List of supported products (P) ROM size (bytes) RAM size Product Package Remarks ROM size for User () (bytes) 32P4B Mask ROM version M37540M2-XXXSP 8192 36P2R-A Mask ROM version M37540M2-XXXFP (8062) Mask ROM version (extended operating temperature version)
  • Page 30 HARDWARE FUNCTIONAL DESCRIPTION FUNCTIONAL DESCRIPTION Stack pointer (S) The stack pointer is an 8-bit register used during subroutine calls Central Processing Unit (CPU) and interrupts. The stack is used to store the current address data The MCU uses the standard 740 family instruction set. Refer to and processor status when branching to subroutines or interrupt the table of 740 family addressing modes and machine-language routines.
  • Page 31 HARDWARE FUNCTIONAL DESCRIPTION On-going Routine Interrupt request (Note) M (S) Execute JSR (S – 1) Store Return Address on Stack M (S) M (S) (S – 1) Store Return Address (S – 1) on Stack Store Contents of Processor M (S) Status Register on Stack M (S) (PS)
  • Page 32 HARDWARE FUNCTIONAL DESCRIPTION Processor status register (PS) (5) Break flag (B) The processor status register is an 8-bit register consisting of The B flag is used to indicate that the current interrupt was gener- flags which indicate the status of the processor after an arithmetic ated by the BRK instruction.
  • Page 33 HARDWARE FUNCTIONAL DESCRIPTION [CPU mode register] CPUM The CPU mode register contains the stack page selection bit. This register is allocated at address 003B16. CPU mode register (CPUM: address 003B , initial value: 80 Processor mode bits (Note 1) b1 b0 Switching method of CPU mode register 0 Single-chip mode Switch the CPU mode register (CPUM) at the head of program af-...
  • Page 34 HARDWARE FUNCTIONAL DESCRIPTION Memory Zero page Special function register (SFR) area The 256 bytes from addresses 0000 to 00FF are called the The SFR area in the zero page contains control registers such as zero page area. The internal RAM and the special function regis- I/O ports and timers.
  • Page 35 HARDWARE FUNCTIONAL DESCRIPTION Port P0 (P0) 0000 0020 Timer Y, Z mode register (TYZM) Port P0 direction register (P0D) 0001 0021 Prescaler Y (PREY) Port P1 (P1) Timer Y secondary (TYS) 0002 0022 Port P1 direction register (P1D) Timer Y primary (TYP) 0003 0023 Port P2 (P2)
  • Page 36 HARDWARE FUNCTIONAL DESCRIPTION I/O Ports [Pull-up control register] PULL [Direction registers] PiD By setting the pull-up control register (address 0016 ), ports P0 The I/O ports have direction registers which determine the input/ and P3 can exert pull-up control by program. However, pins set to output direction of each pin.
  • Page 37 HARDWARE FUNCTIONAL DESCRIPTION Table 5 I/O port function table Name Input/output I/O format Non-port function Related SFRs Diagram No. /CNTR I/O port P0 I/O individual •CMOS compatible Key input interrupt Pull-up control register bits Timer X function output input level Timer Y mode register Timer Y function output Timer Z mode register...
  • Page 38 HARDWARE FUNCTIONAL DESCRIPTION (1)Port P0 (2)Ports P0 Pull-up control Pull-up control Direction Direction register register Data bus Port latch Port latch Data bus Pulse output mode CNTR interrupt input Timer output To key input interrupt key-on wakeup generating circuit To key input interrupt selection bit generating circuit (3)Port P0...
  • Page 39 HARDWARE FUNCTIONAL DESCRIPTION (8) Port P1 (9) Port P1 output in operation signal DATA2 pin selection bit DATA2 Direction Serial I/O mode selection bit Serial I/O1 enable bit register output enable bit RDY1 Direction Port register Data bus latch Data bus Port latch Pulse output mode , P1...
  • Page 40 HARDWARE FUNCTIONAL DESCRIPTION Interrupts Notes on use Interrupts occur by 15 different sources : 5 external sources, 9 in- When setting the followings, the interrupt request bit may be set to ternal sources and 1 software source. “1”. •When switching external interrupt active edge Interrupt control Related register: Interrupt edge selection register (address All interrupts except the BRK instruction interrupt have an interrupt...
  • Page 41 HARDWARE FUNCTIONAL DESCRIPTION Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Interrupt request Reset Fig. 19 Interrupt control Interrupt edge selection register (INTEDGE : address 003A , initial value : 00 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active interrupt edge selection bit 0 : Falling edge active...
  • Page 42 HARDWARE FUNCTIONAL DESCRIPTION Key Input Interrupt (Key-On Wake-Up) A key-on wake-up interrupt request is generated by applying “L” level to any pin of port P0 that has been set to input mode. In other words, it is generated when the AND of input level goes from “1”...
  • Page 43 HARDWARE FUNCTIONAL DESCRIPTION Timer A Timers The 7540 Group has 5 timers: timer 1, timer A, timer X, timer Y Timer A is a 16-bit timer and counts the signal which is the oscil- and timer Z. lation frequency divided by 16. When Timer A underflows, the timer A interrupt request bit is set to “1”.
  • Page 44 HARDWARE FUNCTIONAL DESCRIPTION Timer X (3) Event counter mode Timer X is an 8-bit timer and counts the prescaler X output. Timer A counts signals input from the P0 /CNTR pin. When Timer X underflows, the timer X interrupt request bit is set Except for this, the operation in event counter mode is the same as in timer mode.
  • Page 45 HARDWARE FUNCTIONAL DESCRIPTION (4) Pulse width measurement mode In the pulse width measurement mode, the pulse width of the sig- Timer X mode register (TXM : address 002B , initial value: 00 nal input to P1 /CNTR pin is measured. Timer X operating mode bits The operation of Timer X can be controlled by the level of the sig- b1 b0...
  • Page 46 HARDWARE FUNCTIONAL DESCRIPTION Timer Y (2) Programmable waveform generation mode Timer Y is an 8-bit timer and counts the prescaler Y output. In the programmable waveform generation mode, timer counts the When Timer Y underflows, the timer Y interrupt request bit is set to setting value of timer Y primary and the setting value of timer Y “1”.
  • Page 47 HARDWARE FUNCTIONAL DESCRIPTION Notes on programmable generation waveform mode • Count set value In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid by writing to TYP because the set- ting to them is executed all at once by writing to TYP. Even when changing TYP is not required, write the same value again.
  • Page 48 HARDWARE FUNCTIONAL DESCRIPTION Timer Z (2) Programmable waveform generation mode Timer Z is an 8-bit timer and counts the prescaler Z output. In the programmable waveform generation mode, timer counts the When Timer Z underflows, the timer Z interrupt request bit is set to setting value of timer Z primary and the setting value of timer Z “1”.
  • Page 49 HARDWARE FUNCTIONAL DESCRIPTION Notes on the programmable waveform generation mode are de- The falling or rising can be selected as the edge of the valid trig- scribed below; ger of INT pin by the INT pin one-shot trigger edge selection bit. Notes on programmable waveform generation mode During the one-shot pulse output interval, the one-shot pulse out- •...
  • Page 50 HARDWARE FUNCTIONAL DESCRIPTION (4) Programmable wait one-shot generation mode Notes on programmable wait one-shot generation mode In the programmable wait one-shot generation mode, the one-shot • Count set value pulse by the setting value of timer Z secondary can be output from In the programmable wait one-shot generation mode, values of pin by software or external trigger to INT pin after the wait...
  • Page 51 HARDWARE FUNCTIONAL DESCRIPTION Timer Y, Z mode register (TYZM : address 0020 , initial value: 00 Timer Y operating mode bit 0 : Timer mode 1 : Programmable waveform generation mode Not used (return “0” when read) Timer Y write control bit 0 : Write to latch and timer simultaneously 1 : Write to only latch Timer Y count stop bit...
  • Page 52 HARDWARE FUNCTIONAL DESCRIPTION Data bus Timer 1 latch (8) Prescaler 1 latch (8) Timer 1 interrupt Prescaler 1 (8) Timer 1 (8) )/16 request bit Pulse width HL continuously measurement mode Rising edge detected Period measurement mode Falling edge detected CNTR active Data bus...
  • Page 53 HARDWARE FUNCTIONAL DESCRIPTION Data bus )/16 Prescaler X latch (8) Timer X latch (8) Pulse width Timer mode measurement Pulse output Timer X count mode mode source selection bits Timer X Timer X (8) Prescaler X (8) interrupt request bit CNTR active Event...
  • Page 54 HARDWARE FUNCTIONAL DESCRIPTION Serial I/O (1) Clock Synchronous Serial I/O Mode Serial I/O1 Clock synchronous serial I/O1 mode can be selected by setting Serial I/O1 can be used as either clock synchronous or asynchro- the serial I/O1 mode selection bit of the serial I/O1 control register nous (UART) serial I/O.
  • Page 55 HARDWARE FUNCTIONAL DESCRIPTION The transmit and receive shift registers each have a buffer, but the (2) Asynchronous Serial I/O (UART) Mode two buffers have the same address in memory. Since the shift reg- Clock asynchronous serial I/O mode (UART) can be selected by ister cannot be written to or read from directly, transmit data is clearing the serial I/O1 mode selection bit of the serial I/O1 control written to the transmit buffer register, and receive data is read...
  • Page 56 HARDWARE FUNCTIONAL DESCRIPTION [Transmit buffer register/receive buffer register (TB/RB)] Notes on serial I/O 0018 • Serial I/O interrupt The transmit buffer register and the receive buffer register are lo- When setting the transmit enable bit to “1”, the serial I/O transmit cated at the same address.
  • Page 57 HARDWARE FUNCTIONAL DESCRIPTION Serial I/O1 status register Serial I/O1 control register (SIO1STS : address 0019 , initial value: 00 (SIO1CON : address 001A , initial value: 00 BRG count source selection bit (CSS) Transmit buffer empty flag (TBE) 0: f(X 0: Buffer full 1: f(X 1: Buffer empty...
  • Page 58 HARDWARE FUNCTIONAL DESCRIPTION Serial I/O2 The serial I/O2 function can be used only for clock synchronous Serial I/O2 control register serial I/O. (SIO2CON: address 0030 , initila value: 00 For clock synchronous serial I/O2 the transmitter and the receiver Internal synchronous clock selection bits must use the same clock.
  • Page 59 HARDWARE FUNCTIONAL DESCRIPTION Serial I/O2 operation By writing to the serial I/O2 register (address 0031 ) the serial I/ O2 counter is set to “7”. After writing, the S pin outputs data every time the transfer DATA2 clock shifts from “H” to “L”. And, as the transfer clock shifts from “L”...
  • Page 60 HARDWARE FUNCTIONAL DESCRIPTION A-D Converter The functional blocks of the A-D converter are described below. A-D control register (ADCON : address 0034 , initial value: 10 Analog input pin selection bits [A-D conversion register] AD 000 : P2 The A-D conversion register is a read-only register that stores the 001 : P2 010 : P2 result of A-D conversion.
  • Page 61 HARDWARE FUNCTIONAL DESCRIPTION Watchdog Timer Operation of watchdog timer H count source selection bit The watchdog timer gives a means for returning to a reset status A watchdog timer H count source can be selected by bit 7 of the when the program fails to run on its normal loop due to a runaway.
  • Page 62 HARDWARE FUNCTIONAL DESCRIPTION Reset Circuit Poweron The microcomputer is put into a reset status by holding the RE- (Note) SET pin at the “L” level for 2 µs or more when the power source Power source voltage RESET voltage is 2.2 to 5.5 V and X is in stable oscillation.
  • Page 63 HARDWARE FUNCTIONAL DESCRIPTION Address Register contents 0001 Port P0 direction register 0003 Port P1 direction register 0005 Port P2 direction register 0007 Port P3 direction register 0016 Pull-up control register 0017 Port P1P3 control register 0019 Serial I/O1 status register 001A Serial I/O1 control register 001B...
  • Page 64 HARDWARE FUNCTIONAL DESCRIPTION Clock Generating Circuit Note: Externally connect a An oscillation circuit can be formed by connecting a resonator be- damping resistor Rd de- M 3 7 5 4 0 tween X and X , and an RC oscillation circuit can be formed p e n d i n g t h e oscillation frequency.
  • Page 65 HARDWARE FUNCTIONAL DESCRIPTION (1) Oscillation control Oscillation stop detection circuit (Note) • Stop mode The oscillation stop detection circuit is used for reset occurrence When the STP instruction is executed, the internal clock φ stops at when a ceramic resonator or an oscillation circuit stops by discon- an “H”...
  • Page 66 HARDWARE FUNCTIONAL DESCRIPTION O U T Main clock division ratio selection bit Middle-, high-, low-speed mode T i m e r 1 Prescaler 1 1 / 4 1 / 2 R i n g o s c i l l a t o r m o d e Main clock division ratio selection bit M i d d l e - s p e e d m o d e...
  • Page 67 HARDWARE FUNCTIONAL DESCRIPTION S t o p m o d e Wait mode I n t e r r u p t instruction I n t e r r u p t I n t e r r u p t instruction W I T i n s t r u c t i o n...
  • Page 68 HARDWARE NOTES ON PROGRAMMING/NOTES ON HARDWARE NOTES ON PROGRAMMING State transition Do not stop the clock selected as the operation clock because of Processor Status Register setting of CM3, 4. The contents of the processor status register (PS) after reset are NOTES ON HARDWARE undefined except for the interrupt disable flag I which is “1”.
  • Page 69 HARDWARE NOTES ON PERIPHERAL FUNCTIONS NOTES ON PERIPHERAL FUNCTIONS Timer Y: Programmable Generation Waveform Mode Interrupt • Count set value When setting the followings, the interrupt request bit may be set to In the programmable waveform generation mode, values of TYS, “1”.
  • Page 70 HARDWARE NOTES ON PERIPHERAL FUNCTIONS Serial I/O Ti m e r Z : P r o g r a m m a b l e O n e - s h o t Generation Mode • Serial I/O interrupt When setting the transmit enable bit to “1”, the serial I/O transmit •...
  • Page 71 HARDWARE NOTES ON PERIPHERAL FUNCTIONS Notes on clock generating circuit For use with the oscillation stabilization set bit after release of the STP instruction set to “1”, set values in timer 1 and prescaler 1 af- ter fully appreciating the oscillation stabilization time of the oscillator to be used.
  • Page 72 HARDWARE DATA REQUIRED FOR MASK ORDERS/DATA REQUIRED FOR ROM PROGRAMMING ORDERS/ ROM PROGRAMMING METHOD DATA REQUIRED FOR MASK ORDERS ROM PROGRAMMING METHOD The following are necessary when ordering a mask ROM produc- The built-in PROM of the blank One Time PROM version can be tion: read or programmed with a general-purpose PROM programmer 1.Mask ROM Order Confirmation Form *...
  • Page 73 HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT when two or more interrupt requests occur during F U N C T I O N A L D E S C R I P T I O N the same sampling, the higher-priority interrupt is SUPPLEMENT accepted first.
  • Page 74 HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT Timing After Interrupt instruction that is currently in execution. Figure 55 shows a timing chart after an interrupt The interrupt processing routine begins with the occurs, and Figure 56 shows the time up to execution machine cycle following the completion of the of the interrupt processing routine.
  • Page 75 HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT A-D Converter By repeating the above operations up to the lowest- order bit of the A-D conversion register, an analog A-D conversion is started by setting AD conversion value converts into a digital value. completion bit to “0.” During A-D conversion, internal A-D conversion completes at 122 clock cycles (20.34 µs at f(X operations are performed as follows.
  • Page 76 HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT Figure 56 shows A-D conversion equivalent circuit, and Figure 57 shows A-D conversion timing chart. (Note 1) 1.5 kΩ(Typical) 1.5 pF(Typical) ANi (i=0 to 7: 36-pin version i=0 to 5: 32-pin version) (Note 2) (Note 1) 12 pF(Typical) Typical voltage Chopper Amp.
  • Page 77 C H A P T E R 2 APPLICATION 2.1 I/O port 2.2 Timer A 2.3 Timer 1 2.4 Timer X 2.5 Timer Y and timer Z 2.6 Serial I/O1 2.7 Serial I/O2 2.8 A-D converter 2.9 Reset...
  • Page 78 APPLICATION 2.1 I/O port 2.1 I/O port This paragraph explains the registers setting method and the notes relevant to the I/O ports. 2.1.1 Memory map Port P0 (P0) 0000 Port P0 direction register (P0D) 0001 Port P1 (P1) 0002 Port P1 direction register (P1D) 0003 Port P2 (P2) 0004...
  • Page 79 APPLICATION 2.1 I/O port 2.1.2 Relevant registers Port Pi b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (Pi) (i = 0, 2, 3) [Address : 00 , 04 , 06 Name Function At reset Port Pi In output mode Write Port latch Port Pi...
  • Page 80 APPLICATION 2.1 I/O port Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i = 0, 2, 3) [Address : 01 , 05 , 07 Name Function At reset 0 : Port Pi input mode Port Pi direction register 1 : Port Pi...
  • Page 81 APPLICATION 2.1 I/O port Pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Pull-up control register (PULL) [Address : 16 Name Function At reset 0 : Pull-up Off pull-up control bit 1 : Pull-up On 0 : Pull-up Off pull-up control bit 1 : Pull-up On 0 : Pull-up Off...
  • Page 82 APPLICATION 2.1 I/O port Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register (INTEDGE) [Address : 3A Function At reset Name 0 : Falling edge active interrupt edge 1 : Rising edge active selection bit interrupt edge 0 : Falling edge active...
  • Page 83 APPLICATION 2.1 I/O port Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E Function Name At reset Serial I/O1 receive 0 : Interrupt disabled 1 : Interrupt enabled interrupt enable bit 0 : Interrupt disabled Serial I/O1 transmit interrupt enable bit...
  • Page 84 APPLICATION 2.1 I/O port R E S E T I n i t i a l i z a t i o n X: This bit is not used here. Set it to “0” or “1” arbitrary. S E I Note: For the concrete time, ask the oscillator manufacture.
  • Page 85 APPLICATION 2.1 I/O port 2.1.4 Application example of key-on wake up (2) Outline: The key-on wakeup interrupt is used as the normal external interrupt. Specifications: The key-on wakeup interrupt occurs by input of the falling edge to port P0i. If necessary, the built-in pull-up resistor is used.
  • Page 86 APPLICATION 2.1 I/O port 2.1.5 Handling of unused pins Table 2.1.1 Handling of unused pins Pins/Ports name Handling P0, P1, P2, P3 •Set to the input mode and connect each to Vcc or Vss through a resistor of 1 kΩ to 10 kΩ.
  • Page 87 APPLICATION 2.1 I/O port 2.1.6 Notes on input and output ports Notes on using input and output ports are described below. (1) Notes in stand-by state In stand-by state* for low-power dissipation, do not make input levels of an input port and an I/O port “undefined”.
  • Page 88 APPLICATION 2.1 I/O port 2.1.7 Termination of unused pins (1) Terminate unused pins I/O ports : • Set the I/O ports for the input mode and connect them to V or V through each resistor of 1 kΩ to 10 kΩ. Ports that permit the selecting of a built-in pull-up resistor can also use this resistor.
  • Page 89 APPLICATION 2.2 Timer A 2.2 Timer A This paragraph explains the registers setting method and the notes relevant to the timer A. 2.2.1 Memory map 0001 Port P0 direction register (P0D) Pull-up control register (PULL) 0016 Timer A mode register (TAM) 001D Timer A (low-order) (TAL) 001E...
  • Page 90 APPLICATION 2.2 Timer A 2.2.2 Relevant registers Port P0 direction register b7 b6 b5 b4 b3 b2 b1 b0 Port P0 direction register (P0D) [Address : 01 Name Function At reset 0 : Port Pi input mode Port P0 direction register 1 : Port Pi output mode 0 : Port Pi...
  • Page 91 APPLICATION 2.2 Timer A Timer A mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer A mode register (TAM) [Address : 1D Function Name At reset Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”. b5 b4 Timer A operating mode bits 0 0 : Timer mode...
  • Page 92 APPLICATION 2.2 Timer A Timer A register (low-order, high-order) b7 b6 b5 b4 b3 b2 b1 b0 Timer A register (low-order, high-order) (TAL, TAH) [Address : 1E , 1F Function At reset •Set a count value of timer A. •The value set in this register is written to both timer A and timer A latch at the same time.
  • Page 93 APPLICATION 2.2 Timer A Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address : 3C Function Name At reset 0 : No interrupt request issued Serial I/O1 receive 1 : Interrupt request issued interrupt request bit 0 : No interrupt request issued Serial I/O1 transmit interrupt...
  • Page 94 APPLICATION 2.2 Timer A Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E Function At reset Name Serial I/O1 receive 0 : Interrupt disabled 1 : Interrupt enabled interrupt enable bit Serial I/O1 transmit interrupt 0 : Interrupt disabled 1 : Interrupt enabled...
  • Page 95 APPLICATION 2.2 Timer A 2.2.3 Timer mode (1) Operation description Timer A counts the oscillation frequency divided by 16. Each time the count clock is input, the contents of Timer A is decremented by 1. When the contents of Timer A reach “0000 ”, an underflow occurs at the next count clock, and the timer A latch is reloaded into Timer A.
  • Page 96 APPLICATION 2.2 Timer A P r o c e s s 1 : D i s a b l e t i m e r A i n t e r r u p t . I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 3 F T i m e r A i n t e r r u p t d i s a b l e d P r o c e s s 2 : S e t t i m e r A m o d e r e g i s t e r .
  • Page 97 APPLICATION 2.2 Timer A (3) Application example of timer mode Outline: The input clock is divided by the timer so that the period processing is executed every 25 ms intervals. Specifications: •The f(X ) = 8 MHz is divided by timer A to detect 25 ms. •The timer A interrupt request is confirmed in the main routine.
  • Page 98 APPLICATION 2.2 Timer A 2.2.4 Period measurement mode (1) Operation description In the period measurement mode, the pulse period input from the P0 /CNTR pin is measured. CNTR interrupt request is generated at rising/falling edge of CNTR pin input signal. Simultaneously, the value in the timer A latch is reloaded in Timer A and count continues.
  • Page 99 APPLICATION 2.2 Timer A P r o c e s s 5 : S e t t h e c o u n t v a l u e t o t i m e r A (N o t e) . •...
  • Page 100 APPLICATION 2.2 Timer A (3) Application example of period measurement mode Outline: The phase control signal is adjusted by using the period measurement mode. Specifications: • The phase control signal is output to a load, and that controls the phase of a load. •...
  • Page 101 APPLICATION 2.2 Timer A RESET X : T h i s b i t i s n o t u s e d h e r e . S e t i t t o “ 0 ” o r “ 1 ” a r b i t r a r y . I n i t i a l i z a t i o n S E I C L D...
  • Page 102 APPLICATION 2.2 Timer A 2.2.5 Event counter mode (1) Operation description Timer A counts signals input from the P0 /CNTR pin. Except for this, the operation in event counter mode is the same as in timer mode. The active edge of CNTR pin input signal can be selected from rising or falling by the CNTR active edge switch bit.
  • Page 103 APPLICATION 2.2 Timer A Process 6: In order to use the CNTR pin function of the P0 /CNTR pin, disable the P0 key-on wakeup function. I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( I N T E D G E ) [ A d d r e s s 3 A Key-on wakeup disabled P r o c e s s 7 : I n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t “...
  • Page 104 APPLICATION 2.2 Timer A (3) Application example of event counter mode Outline: The frequency of the pulse which is input to the P0 /CNTR pin (“H” active) is measured by the number of events in a certain period. Specifications: The count source of timer A is input from the P0 /CNTR pin, and the timer A starts counting the count source.
  • Page 105 APPLICATION 2.2 Timer A RESET I n i t i a l i z a t i o n X : T h i s b i t i s n o t u s e d h e r e . S e t i t t o “ 0 ” o r “ 1 ” a r b i t r a r y . S E I C L D C L T...
  • Page 106 APPLICATION 2.2 Timer A 2.2.6 Pulse width HL continuously measurement mode (1) Operation description In the pulse width HL continuously measurement mode, the pulse width (“H” and “L” levels) input to the P0 /CNTR pin is measured. CNTR interrupt request is generated at both rising and falling edges of CNTR pin input signal.
  • Page 107 APPLICATION 2.2 Timer A P r o c e s s 6 : I n o r d e r t o u s e t h e C N T R p i n f u n c t i o n o f t h e P 0 / C N T R p i n , d i s a b l e t h e P 0 k e y - o n w a k e u p f u n c t i o n .
  • Page 108 APPLICATION 2.2 Timer A (3) Application example of pulse width HL continuously measurement mode Outline: A telephone ringing (calling) pulse* is detected by using the pulse width HL continuously measurement mode. * Signal which is sent by turning on/off (make/break) the telephone line. Each country has a different standard.
  • Page 109 APPLICATION 2.2 Timer A R E S E T I n i t i a l i z a t i o n X: This bit is not used here. Set it to “0” or “1” arbitrary. S E I C L D C L T ←...
  • Page 110 APPLICATION 2.2 Timer A C N T R i n t e r r u p t p r o c e s s i n g r o u t i n e L e v e l o f P 0 / C N T R i s c h e c k e d , a n d w h i c h d u r a t i o n m e a s u r i n g i s f i n i s h e d i s j u d g e d .
  • Page 111 APPLICATION 2.2 Timer A 2.2.7 Notes on timer A Notes on using timer A are described below. (1) Common to all modes When reading timer A (high-order) (TAH) and timer A (low-order) (TAL), the contents of timer A is read out. Read both registers in order of TAH and TAL following, certainly. TAH and TAL keep the values until they are read out.
  • Page 112 APPLICATION 2.3 Timer 1 2.3 Timer 1 This paragraph explains the registers setting method and the notes relevant to the timer 1. 2.3.1 Memory map 0028 Prescaler 1 (PRE1) Timer 1 (T1) 0029 0038 MISRG 003D Interrupt request register 2 (IREQ2) Interrupt control register 2 (ICON2) 003F Fig.
  • Page 113 APPLICATION 2.3 Timer 1 Timer 1 b7 b6 b5 b4 b3 b2 b1 b0 Timer 1 (T1) [Address : 29 Function At reset •Set a count value of timer 1. •The value set in this register is written to both timer 1 and timer 1 latch at the same time.
  • Page 114 APPLICATION 2.3 Timer 1 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address : 3D Function Name At reset Timer Y interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued Timer Z interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued...
  • Page 115 APPLICATION 2.3 Timer 1 2.3.3 Timer 1 operation description Timer 1 always operates in the timer mode. Prescaler 1 counts the selected count source. Each time the count clock is input, the contents of Prescaler 1 is decremented by 1. When the contents of Prescaler 1 reach “00 ”, an underflow occurs at the next count clock, and the prescaler 1 latch is reloaded into Prescaler 1 and count continues.
  • Page 116 APPLICATION 2.4 Timer X 2.4 Timer X This paragraph explains the registers setting method and the notes relevant to the timer X. 2.4.1 Memory map 0001 Port P0 direction register (P0D) 0003 Port P1 direction register (P1D) Timer X mode register (TXM) 002B Prescaler X (PREX) 002C...
  • Page 117 APPLICATION 2.4 Timer X 2.4.2 Relevant registers Port P0 direction register b7 b6 b5 b4 b3 b2 b1 b0 Port P0 direction register (P0D) [Address : 01 Name Function At reset 0 : Port Pi input mode Port P0 direction register 1 : Port Pi output mode 0 : Port Pi...
  • Page 118 APPLICATION 2.4 Timer X Timer X mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register (TXM) [Address : 2B Function At reset Name b1 b0 Timer X operating mode bits 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement...
  • Page 119 APPLICATION 2.4 Timer X Prescaler X b7 b6 b5 b4 b3 b2 b1 b0 Prescaler X (PREX) [Address : 2C Function At reset •Set a count value of prescaler X. •The value set in this register is written to both prescaler X and the prescaler X latch at the same time.
  • Page 120 APPLICATION 2.4 Timer X Timer count source set register b7 b6 b5 b4 b3 b2 b1 b0 Timer count source set register (TCSS) [Address : 2E Function Name At reset Timer X count source b1 b0 0 0 : f(X )/16 selection bits 0 1 : f(X...
  • Page 121 APPLICATION 2.4 Timer X Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address : 3C Function Name At reset Serial I/O1 receive 0 : No interrupt request issued 1 : Interrupt request issued interrupt request bit Serial I/O1 transmit interrupt 0 : No interrupt request issued...
  • Page 122 APPLICATION 2.4 Timer X 2.4.3 Timer mode (1) Operation description Prescaler X counts the selected count source by the timer X count source selection bits. Each time the count clock is input, the contents of Prescaler X is decremented by 1. When the contents of Prescaler X reach “00 ”, an underflow occurs at the next count clock, and the prescaler X latch is reloaded into Prescaler X and count continues.
  • Page 123 APPLICATION 2.4 Timer X P r o c e s s 1 : D i s a b l e t i m e r X i n t e r r u p t . Interrupt control register 1 (ICON1) [Address 3E Timer X interrupt disabled P r o c e s s 2 : S e t t i m e r X m o d e r e g i s t e r .
  • Page 124 APPLICATION 2.4 Timer X (3) Application example of timer mode Outline: The input clock is divided by the timer so that the clock is counted up every 250 ms intervals. Specifications: •The f(X ) = 4.19 MHz (2 Hz) is divided by timer X. •The clock is counted up in the timer X interrupt processing routine (timer X interrupt occurs every 250 ms).
  • Page 125 APPLICATION 2.4 Timer X R E S E T I n i t i a l i z a t i o n X: This bit is not used here. Set it to “0” or “1” arbitrary. S E I C L D C L T ←...
  • Page 126 APPLICATION 2.4 Timer X 2.4.4 Pulse output mode (1) Operation description In the pulse output mode, the waveform whose polarity is inverted each time timer X underflows is output from the P1 CNTR pin. The output level of CNTR pin can be selected by the CNTR active edge switch bit.
  • Page 127 APPLICATION 2.4 Timer X P r o c e s s 5 : S e t t i m e r c o u n t s o u r c e s e t r e g i s t e r . T i m e r c o u n t s o u r c e s e t r e g i s t e r ( T C S S ) [ A d d r e s s 2 E T i m e r X c o u n t s o u r c e s e l e c t i o n b i t s b 1 b 0...
  • Page 128 APPLICATION 2.4 Timer X (3) Application example of pulse output mode Outline: The pulse output mode of timer X is used for a piezoelectric buzzer output. Specifications: The rectangular waveform which is clock f(X ) = 4 MHz divided up to 4 kHZ is output from the P1 /CNTR pin.
  • Page 129 APPLICATION 2.4 Timer X R E S E T X : T h i s b i t i s n o t u s e d h e r e . S e t i t t o “ 0 ” o r “ 1 ” a r b i t r a r y . I n i t i a l i z a t i o n S E I C L D...
  • Page 130 APPLICATION 2.4 Timer X 2.4.5 Event counter mode (1) Operation description The timer X counts signals input from the P1 /CNTR pin. Except for this, the operation in event counter mode is the same as in timer mode. The active edge of CNTR pin input signal can be selected from rising or falling by the CNTR active edge switch bit.
  • Page 131 APPLICATION 2.4 Timer X P r o c e s s 5 : S e t t h e c o u n t v a l u e t o t i m e r X . • S e t t h e c o u n t v a l u e t o p r e s c a l e r X a n d t i m e r X P r e s c a l e r X ( P R E X ) ( A d d r e s s 2 C C o u n t v a l u e T i m e r X ( T X ) ( A d d r e s s 2 D...
  • Page 132 APPLICATION 2.4 Timer X (3) Application example of event counter mode Outline: Pulses generated corresponding to the water flow rate are counted for a fixed period (100 ms), and the water flow rate during this period is calculated. Specifications: Pulses generated corresponding to the water flow rate are input to the P1 /CNTR pin and counted using timer X.
  • Page 133 APPLICATION 2.4 Timer X F l o w r a t e m e a s u r i n g r o u t i n e S e t “ 0 ” t o t h e C N T R i n t e r r u p t e n a b l e b i t .
  • Page 134 APPLICATION 2.4 Timer X 2.4.6 Pulse width measurement mode (1) Operation description In the pulse width measurement mode, the pulse width of the signal input to P1 /CNTR pin is measured. The operation of Timer X can be controlled by the level of the signal input from the CNTR pin.
  • Page 135 APPLICATION 2.4 Timer X P r o c e s s 5 : S e t t h e c o u n t v a l u e t o t i m e r X . • S e t t h e i n i t i a l v a l u e t o p r e s c a l e r X a n d t i m e r X Prescaler X (PREX) (Address 2C I n i t i a l v a l u e Timer X (TX) (Address 2D...
  • Page 136 APPLICATION 2.4 Timer X (3) Application example of pulse width measurement mode Outline: “H” level width of pulse input to P1 /CNTR pin is counted. Specifications: The “H” level width of a FG pulse input to the P1 /CNTR pin is counted. An underflow is detected by the timer X interrupt.
  • Page 137 APPLICATION 2.4 Timer X R E S E T I n i t i a l i z a t i o n X: This bit is not used here. Set it to “0” or “1” arbitrary. S E I C L D C L T ←...
  • Page 138 APPLICATION 2.4 Timer X 2.4.7 Notes on timer X Notes on using each mode of timer X are described below. (1) Count source ) can be used only when a ceramic oscillator or a ring oscillator is used. Do not use f(X ) at RC oscillation.
  • Page 139 APPLICATION 2.5 Timer Y and timer Z 2.5 Timer Y and timer Z This paragraph explains the registers setting method and the notes relevant to the timer Y and timer Z. 2.5.1 Memory map Port P0 direction register (P0D) 0001 Port P3 direction register (P3D) 0007 Pull-up control register (PULL)
  • Page 140 APPLICATION 2.5 Timer Y and timer Z 2.5.2 Relevant registers Port P0 direction register b7 b6 b5 b4 b3 b2 b1 b0 Port P0 direction register (P0D) [Address : 01 Name Function At reset 0 : Port Pi input mode Port P0 direction register 1 : Port Pi output mode...
  • Page 141 APPLICATION 2.5 Timer Y and timer Z Pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Pull-up control register (PULL) [Address : 16 Name Function At reset 0 : Pull-up Off pull-up control bit 1 : Pull-up On 0 : Pull-up Off pull-up control bit 1 : Pull-up On...
  • Page 142 APPLICATION 2.5 Timer Y and timer Z Timer Y, Z mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z mode register (TYZM) [Address : 20 Function Name At reset Timer Y operating mode bit 0 : Timer mode 1 : Programmable waveform generation mode Nothing is allocated for this bit.
  • Page 143 APPLICATION 2.5 Timer Y and timer Z Timer Y secondary, Timer Z secondary b7 b6 b5 b4 b3 b2 b1 b0 Timer Y secondary, Timer Z secondary (TYS, TZS) [Address : 22 , 26 Function At reset •Set a count value of the corresponding timer. •The value set in this register is written to the corresponding secondary latch at the same time.
  • Page 144 APPLICATION 2.5 Timer Y and timer Z Timer Y, Z waveform output control register b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z waveform output control register (PUM) [Address : 24 Function Name At reset Timer Y primary waveform 0 : Waveform not extended 1 : Waveform extended extension control bit...
  • Page 145 APPLICATION 2.5 Timer Y and timer Z Timer count source set register b7 b6 b5 b4 b3 b2 b1 b0 Timer count source set register (TCSS) [Address : 2E Function Name At reset Timer X count source b1 b0 0 0 : f(X )/16 selection bits 0 1 : f(X...
  • Page 146 APPLICATION 2.5 Timer Y and timer Z CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) [Address : 3B Function Name At reset b1 b0 Processor mode bits ( Note 1) 0 0 : Single-chip mode 0 1 : Not available 1 0 : Not available 1 1 : Not available...
  • Page 147 APPLICATION 2.5 Timer Y and timer Z Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address : 3C Function Name At reset 0 : No interrupt request issued Serial I/O1 receive interrupt request bit 1 : Interrupt request issued Serial I/O1 transmit interrupt...
  • Page 148 APPLICATION 2.5 Timer Y and timer Z Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E Function Name At reset Serial I/O1 receive 0 : Interrupt disabled interrupt enable bit 1 : Interrupt enabled Serial I/O1 transmit interrupt 0 : Interrupt disabled...
  • Page 149 APPLICATION 2.5 Timer Y and timer Z 2.5.3 Timer mode (timer Y and timer Z) The basic operation of Timer Y and Timer Z are the same. In this section, Timer Y is explained. (1) Operation description Prescaler Y counts the count source selected by the timer Y count source selection bits. Each time the count clock is input, the contents of Prescaler Y is decremented by 1.
  • Page 150 APPLICATION 2.5 Timer Y and timer Z P r o c e s s 1 : D i s a b l e t i m e r Y i n t e r r u p t . I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 3 F T i m e r Y i n t e r r u p t d i s a b l e d P r o c e s s 2 : S e t t i m e r Y , Z m o d e r e g i s t e r .
  • Page 151 APPLICATION 2.5 Timer Y and timer Z (3) Application example of timer mode Outline: Pulses generated corresponding to the water flow rate are counted for a fixed period (100 ms), and the water flow rate during this period is calculated. Specifications: Pulses generated corresponding to the water flow rate are input to the P1 /CNTR pin and counted using timer X.
  • Page 152 APPLICATION 2.5 Timer Y and timer Z F l o w r a t e m e a s u r i n g r o u t i n e S e t “ 0 ” t o t h e C N T R i n t e r r u p t e n a b l e b i t .
  • Page 153 APPLICATION 2.5 Timer Y and timer Z 2.5.4 Programmable waveform generation mode (timer Y and timer Z) The basic operation of Timer Y and Timer Z are the same. In this section, Timer Y is explained. (1) Operation description In the programmable waveform generation mode, timer counts the setting value of timer Y primary (TYP) and the setting value of timer Y secondary (TYS) alternately, the waveform whose polarity is inverted each time Timer Y underflows is output from P0 pin.
  • Page 154 APPLICATION 2.5 Timer Y and timer Z Notes 1: In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid by writing to TYP because the setting to them is executed all at once by writing to TYP.
  • Page 155 APPLICATION 2.5 Timer Y and timer Z W h e n “ 0 3 ” i s s e t t o T Y P a n d “ 0 2 ” i s s e t t o T Y S . T i m e r Y c o u n t c l o c k “...
  • Page 156 APPLICATION 2.5 Timer Y and timer Z (2) Programmable waveform generation mode setting method Figure 2.5.24 and Figure 2.5.25 show the setting method for programmable waveform generation mode of timer Y. When timer Z is used, registers are set by the same method. P r o c e s s 1 : D i s a b l e t i m e r Y i n t e r r u p t .
  • Page 157 APPLICATION 2.5 Timer Y and timer Z P r o c e s s 5 : S e t t i m e r Y c o u n t s o u r c e (N o t e 1) . T i m e r c o u n t s o u r c e s e t r e g i s t e r ( T C S S ) [ A d d r e s s 2 E Timer Y count source selection bits b3 b2...
  • Page 158 APPLICATION 2.5 Timer Y and timer Z (3) Application example of programmable waveform generation mode Outline: The waveform extension function is used and the waveform output is executed. Specifications: The “H” width generated by TYP and the “L” width generated by TYS are output. Set each waveform extension function to be valid, and set the duty ratio to be 2:1.
  • Page 159 APPLICATION 2.5 Timer Y and timer Z R E S E T I n i t i a l i z a t i o n X : T h i s b i t i s n o t u s e d h e r e . S e t i t t o “ 0 ” o r “ 1 ” a r b i t r a r y . ←...
  • Page 160 APPLICATION 2.5 Timer Y and timer Z 2.5.5 Programmable one-shot generation mode (timer Z) (1) Operation description In the programmable one-shot generation mode, the one-shot pulse by the setting value of timer Z primary can be output from P0 pin by software or external trigger to the P3 /INT pin.
  • Page 161 APPLICATION 2.5 Timer Y and timer Z W h e n “ 0 3 ” i s s e t t o T Z P T i m e r Z c o u n t c l o c k “...
  • Page 162 APPLICATION 2.5 Timer Y and timer Z (2) Event counter mode setting method Figure 2.5.29 to Figure 2.5.31 show the setting method for programmable one-shot generation mode of timer Z. P r o c e s s 1 : D i s a b l e t h e i n t e r r u p t . I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 3 E interrupt disabled I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 3 F...
  • Page 163 APPLICATION 2.5 Timer Y and timer Z Process 5: When the trigger by INT pin input is selected: Set port P3 direction register, pull-up control register and port P1P3 control register P o r t P 3 d i r e c t i o n r e g i s t e r ( P 3 D ) [ A d d r e s s 0 7 S e t P 3 / I N T p i n a s t h e i n p u t m o d e...
  • Page 164 APPLICATION 2.5 Timer Y and timer Z P r o c e s s 9 : I n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t “...
  • Page 165 APPLICATION 2.5 Timer Y and timer Z (3) Application example of programmable one-shot generation mode Outline: The phase control signal to the load is output by using the programmable one-shot generation mode of Timer Z. Specifications: The phase control signal to the load is output from the P0 pin using the programmable one-shot generation mode of timer Z.
  • Page 166 APPLICATION 2.5 Timer Y and timer Z R E S E T X : T h i s b i t i s n o t u s e d h e r e . S e t i t t o “ 0 ” o r “ 1 ” a r b i t r a r y . I n i t i a l i z a t i o n S E I C L D...
  • Page 167 APPLICATION 2.5 Timer Y and timer Z 2.5.6 Programmable wait one-shot generation mode (timer Z) (1) Operation description In the programmable wait one-shot generation mode, the one-shot pulse by the setting value of timer Z secondary (TZS) can be output from P0 pin by software or external trigger to P3 /INT after the wait by the setting value of the timer Z primary (TZP).
  • Page 168 APPLICATION 2.5 Timer Y and timer Z Notes 1: In the programmable wait one-shot generation mode, values of TZS, EXPZP and EXPZS are valid by writing to TZP. Even when changing TZP is not required, write the same value again. 2: In the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow during the secondary interval simultaneously.
  • Page 169 APPLICATION 2.5 Timer Y and timer Z W h e n “ 0 3 ” i s s e t t o T Z P a n d “ 0 4 ” i s s e t t o T Z S . Timer Z count clock “...
  • Page 170 APPLICATION 2.5 Timer Y and timer Z (2) Programmable wait one-shot generation mode setting method Figure 2.5.36 to Figure 2.5.38 show the setting method for programmable wait one-shot generation mode of Timer Z. P r o c e s s 1 : D i s a b l e i n t e r r u p t . I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 3 E I N T 0 i n t e r r u p t d i s a b l e d Interrupt control register 2 (ICON2) [Address 3F...
  • Page 171 APPLICATION 2.5 Timer Y and timer Z P r o c e s s 5 : W h e n t h e t r i g g e r b y I N T p i n i n p u t i s s e l e c t e d : S e t p o r t P 3 d i r e c t i o n r e g i s t e r , p u l l - u p c o n t r o l r e g i s t e r a n d p o r t P 1 P 3 c o n t r o l r e g i s t e r P o r t P 3 d i r e c t i o n r e g i s t e r ( P 3 D ) [ A d d r e s s 0 7 S e t P 3...
  • Page 172 APPLICATION 2.5 Timer Y and timer Z P r o c e s s 8 : S e t t h e s t a n d b y s t a t e t o a c c e p t t h e o n e - s h o t s t a r t t r i g g e r (N o t e) . T i m e r Y , Z m o d e r e g i s t e r ( T Y Z M ) [ A d d r e s s 2 0 T i m e r Z c o u n t s t a r t N o t e : W h e n t h e I N T...
  • Page 173 APPLICATION 2.5 Timer Y and timer Z (3) Application example of programmable wait one-shot generation mode Outline: The wait one-shot pulse synchronized with the PWM waveform output from the P0 pin is generated from Timer Z by using the programmable waveform generation mode of Timer Y.
  • Page 174 APPLICATION 2.5 Timer Y and timer Z W a i t o n e - s h o t g e n e r a t i o n r o u t i n e S e t “ 0 ” t o t h e t i m e r Z i n t e r r u p t e n a b l e b i t . ( T i m e r Z i n t e r r u p t d i s a b l e d ) T i m e r Z i n t e r r u p t p r o c e s s i n g r o u t i n e S e t t i m e r Y , Z m o d e r e g i s t e r...
  • Page 175 APPLICATION 2.5 Timer Y and timer Z 2.5.7 Notes on timer Y and timer Z Notes on using each mode of Timer Y and Timer Z are described below. (1) Timer mode (timer Y and timer Z) In the timer mode, TYP and TYS is not used. (2) Programmable waveform generation mode (timer Y and timer Z) In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid by writing to TYP because the setting to them is executed all at once by writing to TYP.
  • Page 176 APPLICATION 2.5 Timer Y and timer Z The waveform extension function by the timer Z waveform extension control bits can be used only when “00 ” is set to Prescaler Z. When the value other than “00 ” is set to Prescaler Z, be sure to set “0” to EXPZP. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used.
  • Page 177 APPLICATION 2.6 Serial I/O1 2.6 Serial I/O1 This paragraph explains the registers setting method and the notes relevant to the serial I/O. 2.6.1 Memory map Transmit/Receive buffer register (TB/RB) 0018 Serial I/O1 status register (SIO1STS) 0019 001A Serial I/O1 control register (SIO1CON) UART control register (UARTCON) 001B Baud rate generator (BRG)
  • Page 178 APPLICATION 2.6 Serial I/O1 Serial I/O1 status register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O1 status register (SIO1STS) [Address : 19 Function Name At reset 0 : Buffer full Transmit buffer empty flag 1 : Buffer empty (TBE) 0 : Buffer empty Receive buffer full flag (RBF)
  • Page 179 APPLICATION 2.6 Serial I/O1 U A R T c o n t r o l r e g i s t e r b 7 b 6 b5 b 4 b 3 b 2 b 1 b 0 U A R T c o n t r o l r e g i s t e r ( U A R T C O N ) [ A d d r e s s : 1 B Function N a m e A t r e s e t...
  • Page 180 APPLICATION 2.6 Serial I/O1 Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address : 3C Function Name At reset Serial I/O1 receive 0 : No interrupt request issued 1 : Interrupt request issued interrupt request bit Serial I/O1 transmit interrupt 0 : No interrupt request issued...
  • Page 181 APPLICATION 2.6 Serial I/O1 2.6.3 Serial I/O1 transfer data format Figure 2.6.9 shows the serial I/O1 transfer data format. Clock L S B f i r s t synchronous serial I/O 1ST-8DATA-1SP L S B M S B 1 S T - 7 D A T A - 1 S P L S B M S B S e r i a l I / O 1...
  • Page 182 APPLICATION 2.6 Serial I/O1 2.6.4 Application example of clock synchronous serial I/O1 For clock synchronous serial I/O1, the transmitter and the receiver use the same clock. Synchronizing with this clock, the transmit operation of the transmitter and the receive operation of the receiver are executed at the same time.
  • Page 183 APPLICATION 2.6 Serial I/O1 (2) Clock synchronous serial I/O setting method Figure 2.6.10 and Figure 2.6.11 show the setting method for the clock synchronous serial I/O1. P r o c e s s 1 : S t o p a n d i n i t i a l i z e s e r i a l I / O . S e r i a l I / O 1 c o n t r o l r e g i s t e r ( S I O 1 C O N ) [ A d d r e s s 1 A T r a n s m i t o p e r a t i o n s t o p a n d i n i t i a l i z e d R e c e i v e o p e r a t i o n s t o p a n d i n i t i a l i z e d...
  • Page 184 APPLICATION 2.6 Serial I/O1 P r o c e s s 5 : I n o r d e r n o t t o e x e c u t e t h e n o r e q u e s t e d i n t e r r u p t p r o c e s s i n g , s e t “ 0 ” ( n o r e q u e s t e d ) t o t h e s e r i a l I / O 1 t r a n s m i t / r e c e i v e i n t e r r u p t r e q u e s t b i t .
  • Page 185 APPLICATION 2.6 Serial I/O1 (3) Communication using clock synchronous serial I/O1 (transmit/receive) Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O1. S RDY1 signal is used for communication control. Specifications : •The serial I/O1 (clock synchronous serial I/O selected ) is used. •Synchronous clock frequency : 125 kHz;...
  • Page 186 APPLICATION 2.6 Serial I/O1 RESET I n i t i a l i z a t i o n S E I C L D C L T S e t s e r i a l I / O 1 c o n t r o l r e g i s t e r 1 1 0 0 0 0 S I O 1 C O N ( A d d r e s s 1 A...
  • Page 187 APPLICATION 2.6 Serial I/O1 R E S E T I n i t i a l i z a t i o n S E I C L D C L T Set serial I/O1 control register 1 1 1 SIO1CON(Address 1A Synchronous clock: External clock input...
  • Page 188 APPLICATION 2.6 Serial I/O1 2.6.5 Application example of clock asynchronous serial I/O1 For clock asynchronous serial I/O1 (UART), the transfer formats used by a transmitter and receiver must be identical. In the 7540 Group, eight serial data transfer formats can be selected. (1) Data transfer rate The transfer bit rate is calculated by the following formula;...
  • Page 189 APPLICATION 2.6 Serial I/O1 (2) UART setting method Figure 2.6.16 and Figure 2.6.17 show the setting method for UART of serial I/O1. P r o c e s s 1 : S t o p a n d i n i t i a l i z e s e r i a l I / O . S e r i a l I / O 1 c o n t r o l r e g i s t e r ( S I O 1 C O N ) [ A d d r e s s 1 A Transmit operation stop and initialization Receive operation stop and initialization...
  • Page 190 APPLICATION 2.6 Serial I/O1 P r o c e s s 4 : S e t U A R T c o n t r o l r e g i s t e r . U A R T c o n t r o l r e g i s t e r ( U A R T C O N ) [ A d d r e s s 1 B S e l e c t c h a r a c t e r l e n g t h 0 : 8 b i t s 1 : 7 b i t s...
  • Page 191 APPLICATION 2.6 Serial I/O1 (3) Communication using UART of serial I/O (transmit/receive) Outline : 2-byte data is transmitted and received, using UART. Port P0 is used for communication control. Specifications : •The Serial I/O1 (UART selected ) is used. •Transfer bit rate : 9600 bps (f(X ) = 4.9152 MHz divided by 512) •Communication control using port P0 (output level of port P0...
  • Page 192 APPLICATION 2.6 Serial I/O1 R E S E T I n i t i a l i z a t i o n S E I C L D C L T S e t s e r i a l I / O 1 c o n t r o l r e g i s t e r 1 0 0 SIO1CON(Address 1A BRG count source: f(X...
  • Page 193 APPLICATION 2.6 Serial I/O1 I n i t i a l i z a t i o n S E I C L D C L T S e t s e r i a l I / O 1 c o n t r o l r e g i s t e r 1 0 1 S I O 1 C O N ( A d d r e s s 1 A BRG count source: f(X...
  • Page 194 APPLICATION 2.6 Serial I/O1 2.6.6 Notes on Serial I/O1 Notes on using serial I/O1 are described below. (1) Notes when selecting clock synchronous serial I/O When the clock synchronous serial I/O1 is used, serial I/O2 cannot be used. When the transmit operation is stopped, clear the serial I/O1 enable bit and the transmit enable bit to “0”...
  • Page 195 APPLICATION 2.6 Serial I/O1 (2) Notes when selecting UART When the clock asynchronous serial I/O1 (UART) is used, serial I/O2 can be used only when BRG output divided by 16 is selected as the synchronous clock. When the transmit operation is stopped, clear the transmit enable bit to “0” (transmit disabled). Reason Same as (1) When the receive operation is stopped, clear the receive enable bit to “0”...
  • Page 196 APPLICATION 2.7 Serial I/O2 2.7 Serial I/O2 This paragraph explains the registers setting method and the notes relevant to the serial I/O. 2.7.1 Memory map Port P1 direction register (P1D) 0003 0030 Serial I/O2 control register (SIO2CON) Serial I/O2 register (SIO2) 0031 Interrupt request register 2 (IREQ2) 003D...
  • Page 197 APPLICATION 2.7 Serial I/O2 S e r i a l I / O 2 c o n t r o l r e g i s t e r b 7 b 6 b5 b 4 b 3 b 2 b 1 b 0 S e r i a l I / O 2 c o n t r o l r e g i s t e r ( S I O 2 C O N ) [ A d d r e s s : 3 0 Function N a m e...
  • Page 198 APPLICATION 2.7 Serial I/O2 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address : 3D Function Name At reset 0 : No interrupt request issued Timer Y interrupt request bit 1 : Interrupt request issued Timer Z interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued...
  • Page 199 APPLICATION 2.7 Serial I/O2 2.7.3 Application example of serial I/O2 (1) Serial I/O2 setting method Figure 2.7.7 and Figure 2.7.8 show the setting method for the serial I/O2. P r o c e s s 1 : D i s a b l e s e r i a l I / O 2 t r a n s m i t / r e c e i v e i n t e r r u p t . Interrupt control register 2 (ICON2) [Address 3F S e r i a l I / O 2 i n t e r r u p t d i s a b l e d P r o c e s s 2 : S e t p o r t P 1 a c c o r d i n g t o t h e u s a g e c o n d i t i o n .
  • Page 200 APPLICATION 2.7 Serial I/O2 Process 5: When the interrupt is used, set “1” (interrupt enabled) to the serial I/O2 interrupt. enable bit. Interrupt control register 2 (ICON2) [Address 3F Serial I/O2 interrupt enabled Process 6: When transmitting, start serial data transmission. Serial I/O2 register (SIO2) [Address 31 S e t t r a n s m i t d a t a Fig.
  • Page 201 APPLICATION 2.7 Serial I/O2 (2) Communication using serial I/O2 (transmit/receive) Outline: 2-byte data is transmitted and received, using the serial I/O2. Port P0 is used for communication control and outputs the quasi-S signal. Specifications: • The serial I/O2, clock synchronous serial I/O, is used. •...
  • Page 202 APPLICATION 2.7 Serial I/O2 R E S E T I n i t i a l i z a t i o n S e t p o r t P 1 t o t h e o u t p u t m o d e . S e t p o r t P 1 t o t h e o u t p u t m o d e .
  • Page 203 APPLICATION 2.7 Serial I/O2 RESET I n i t i a l i z a t i o n S E I C L D C L T S e t q u a s i - S s i g n a l p o r t P 0 t o t h e o u t p u t m o d e .
  • Page 204 APPLICATION 2.7 Serial I/O2 2.7.4 Notes on serial I/O2 Notes on using serial I/O2 are described below. (1) Note on serial I/O1 Serial I/O2 can be used only when serial I/O1 is not used or serial I/O1 is used as UART and the BRG output divided by 16 is selected as the synchronous clock.
  • Page 205 APPLICATION 2.8 A-D converter 2.8 A-D converter This paragraph explains the registers setting method and the notes relevant to the A-D converter. 2.8.1 Memory map A-D control register (ADCON) 0034 A-D conversion register (low-order) (ADL) 0035 0036 A-D conversion register (high-order) (ADH) Interrupt request register 2 (IREQ2) 003D Interrupt control register 2 (ICON2)
  • Page 206 APPLICATION 2.8 A-D converter A-D conversion register (low-order) b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion register (low-order) (ADL) [Address : 35 Function At reset The read-only register in which the A-D conversion’s results are stored. < 8-bit read> b8 b7 b6 b5 b4 b3 <...
  • Page 207 APPLICATION 2.8 A-D converter Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address : 3D Function Name At reset Timer Y interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued Timer Z interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued...
  • Page 208 APPLICATION 2.8 A-D converter 2.8.3 A-D converter application examples (1) Setting of A-D converter Figure 2.8.7 shows the relevant registers setting. P r o c e s s 1 : D i s a b l e A - D c o n v e r s i o n i n t e r r u p t . I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 3 F A - D c o n v e r s i o n i n t e r r u p t d i s a b l e d P r o c e s s 2 : S e t A - D c o n t r o l r e g i s t e r .
  • Page 209 APPLICATION 2.8 A-D converter (2) Control procedure Outline : The analog input voltage input from a sensor is converted to digital values. Specifications : •The analog input voltage input from a sensor is converted to digital values. •P2 pin is used as an analog input pin. Figure 2.8.8 shows a connection diagram, and Figure 2.8.9 shows an example of control procedure.
  • Page 210 APPLICATION 2.8 A-D converter 2.8.4 Notes on A-D converter Notes on A-D converter are described below. (1) Analog input pin Figure 2.8.10 shows the internal equivalent circuit of an analog input. In order to execute the A-D conversion correctly, to complete the charge to an internal capacitor within the specified time is required.
  • Page 211 APPLICATION 2.9 Oscillation control 2.9 Oscillation control This paragraph explains the registers setting method and the notes relevant to the oscillation control. 2.9.1 Memory map MISRG 0038 0039 Watchdog timer control register (WDTCON) CPU mode register (CPUM) 003B Fig. 2.9.1 Memory map of registers relevant to oscillation control 2.9.2 Relevant registers M I S R G b7 b6 b5 b4 b3 b2 b1 b0...
  • Page 212 APPLICATION 2.9 Oscillation control Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer control register (WDTCON) [Address : 39 Name Function At reset Watchdog timer H (The high-order 6 bits are read-only bits.) 0 : STP instruction enabled STP instruction disable bit 1 : STP instruction disabled Watchdog timer H count...
  • Page 213 APPLICATION 2.9 Oscillation control 2.9.3 Application example of ring oscillator The ring oscillator is the oscillation circuit which is equipped with the 7540 Group. External circuits can be eliminated by using this oscillator as the operation clock or by using this oscillator with a ceramic or RC oscillation circuit.
  • Page 214 APPLICATION 2.9 Oscillation control R E S E T I n i t i a l i z a t i o n S E I C L D C L T S e t C P U m o d e r e g i s t e r C P U M ( A d d r e s s 3 B S i n g l e - c h i p m o d e R i n g o s c i l l a t o r o s c i l l a t i o n e n a b l e d...
  • Page 215 APPLICATION 2.9 Oscillation control 2.9.4 Oscillation stop detection circuit The oscillation stop detection circuit can be used to detect the stop by some failure or disconnection of an external ceramic oscillation circuit. In this section, the setting method and application example. (1) Operation description When the stop of an external oscillation circuit is detected by the oscillation stop detection circuit, the oscillation stop detection status bit of MISRG is set to “1”...
  • Page 216 APPLICATION 2.9 Oscillation control (2) Setting method Figure 2.9.7 shows the initial setting method oscillation stop detection circuit. Figure 2.9.8 shows the setting method for the oscillation stop detection circuit in the main processing. * E x e c u t e t h e f o l l o w i n g s e t a t t h e b e g i n n i n g o f p r o g r a m a f t e r s y s t e m i s r e l e a s e d f r o m r e s e t . P r o c e s s 1 : C h e c k t h a t r e s e t b y o s c i l l a t i o n s t o p d e t e c t i o n i s e x e c u t e d b y r e f e r r i n g t h e o s c i l l a t i o n s t o p d e t e c t i o n s t a t u s b i t .
  • Page 217 APPLICATION 2.9 Oscillation control P r o c e s s : S t a r t r i n g o s c i l l a t i o n w h e n i t i s s t o p p e d . CPU mode register (CPUM) [Address 3B R i n g o s c i l l a t i o r o s c i l l a t i o n e n a b l e d P r o c e s s 2 : S e t c e r a m i c o r R C o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n a c t i v e b i t .
  • Page 218 APPLICATION 2.9 Oscillation control 2.9.5 State transition In the 7540 Group, the operation clock is selected from the following 4 types. • f(X )/2 (high-speed mode) • f(X )/8 (middle-speed mode) • Ring oscillator • f(X ) (double-speed mode) (Note 1) Note 1: f(X ) can be used only at the ceramic oscillation.
  • Page 219 APPLICATION 2.9 Oscillation control (1) Example of control procedure Outline: The ring oscillator is used, and the intermittent operation for the low-power dissipation can be realized. Specifications: A mode is selected from the following modes 1 to 4 according to the usage condition. The return from mode 1 is executed by the timer A interrupt request which occurs every 0.5 s.
  • Page 220 APPLICATION 2.9 Oscillation control R E S E T I n i t i a l i z a t i o n S E I C L D O p e r a t i o n m o d e b y c e r a m i c o s c i l l a t i o n C L T Mode 3 S e t C P U m o d e r e g i s t e r...
  • Page 221 APPLICATION 2.9 Oscillation control 2.9.6 Notes on oscillation stop detection circuit Notes on using oscillation stop detection circuit are described below. (1) Note on ring oscillator The 7540 Group starts operation by the ring oscillator. (2) Notes on oscillation circuit stop detection circuit When the stop mode is used, set the oscillation stop detection function to “invalid”.
  • Page 222 APPLICATION 2.9 Oscillation control When the ring oscillation is used as the operation clock, the CPU clock division ratio is the middle- speed mode. When the state transition state 2→state 3→state 4 is performed, execute the NOP instruction as shown below according to the division ratio of CPU clock. →10 •...
  • Page 223 C H A P T E R 3 APPENDIX 3.1 Electrical characteristics 3.2 Typical characteristics 3.3 Notes on use 3.4 Countermeasures against noise 3.5 List of registers 3.6 Package outline 3.7 List of instruction code 3.8 Machine instructions 3.9 SFR memory map 3.10 Pin configurations 3.11 Differences between 7540 Group and 7531 Group...
  • Page 224 APPENDIX 3.1 Electrical characteristics 3.1 Electrical characteristics 3.1.1 7540 Group (General purpose) Applied to: M37540M2-XXXFP/SP/GP, M37540M4-XXXFP/SP/GP, M37540E2FP/SP/GP, M37540E8FP/SP/GP (1) Absolute Maximum Ratings (General purpose) Table 3.1.1 Absolute maximum ratings Parameter Conditions Ratings Symbol Unit Power source voltage –0.3 to 6.5 (Note 1) Input voltage –0.3 to V + 0.3...
  • Page 225 APPENDIX 3.1 Electrical characteristics (2) Recommended Operating Conditions (General purpose) Table 3.1.2 Recommended operating conditions (1) = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max. Power source voltage (ceramic) ) = 8 MHz (High-, Middle-speed mode) ) = 4 MHz (High-, Middle-speed mode) ) = 2 MHz (High-, Middle-speed mode)
  • Page 226 APPENDIX 3.1 Electrical characteristics Table 3.1.3 Recommended operating conditions (2) = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max. “H” peak output current (Note 1) –P0 , P1 –P1 , P2 –P2...
  • Page 227 APPENDIX 3.1 Electrical characteristics (3) Electrical Characteristics (General purpose) Table 3.1.4 Electrical characteristics (1) = 2.2 to 5.5 V, V = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min. Typ. Max.
  • Page 228 APPENDIX 3.1 Electrical characteristics Table 3.1.5 Electrical characteristics (2) = 2.2 to 5.5 V, V = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min. Typ. Max. Power source One Time PROM High-speed mode, f(X ) = 8 MHz Output transistors “off”...
  • Page 229 APPENDIX 3.1 Electrical characteristics (4) A-D Converter Characteristics (General purpose) Table 3.1.6 A-D Converter characteristics = 2.7 to 5.5 V, V = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min. Typ.
  • Page 230 APPENDIX 3.1 Electrical characteristics (5) Timing Requirements (General purpose) Table 3.1.7 Timing requirements (1) = 4.0 to 5.5 V, V = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max. µs (RESET) Reset input “L”...
  • Page 231 APPENDIX 3.1 Electrical characteristics Table 3.1.9 Timing requirements (3) = 2.2 to 5.5 V, V = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max. µs (RESET) Reset input “L” pulse width External clock input cycle time External clock input “H”...
  • Page 232 APPENDIX 3.1 Electrical characteristics (6) Switching Characteristics (General purpose) Table 3.1.10 Switching characteristics (1) = 4.0 to 5.5 V, V = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max. Serial I/O1 clock output “H” pulse width )/2–30 CLK1 CLK1...
  • Page 233 APPENDIX 3.1 Electrical characteristics Table 3.1.12 Switching characteristics (3) = 2.2 to 5.5 V, V = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max. Serial I/O1 clock output “H” pulse width )/2–70 CLK1 CLK1...
  • Page 234 APPENDIX 3.1 Electrical characteristics (CNTR (CNTR (CNTR CNTR 0.8V 0.2V (CNTR (CNTR (CNTR 0.8V CNTR 0.2V (CNTR (CNTR , INT 0.8V 0.2V (RESET) 0.8V RESET 0.2V 0.8V 0.2V CLK1 CLK1 CLK1 0.8V CLK1 0.2V (RxD -RxD CLK1 CLK1 0.8V (at receive) 0.2V -TxD CLK1...
  • Page 235 APPENDIX 3.1 Electrical characteristics 3.1.2 7540Group (Extended operating temperature version) Applied to: M37540M2T-XXXFP/GP, M37540M4T-XXXFP/GP, M37540E8T-XXXFP/GP (2) Absolute Maximum Ratings (Extended operating temperature version) Table 3.1.13 Absolute maximum ratings Symbol Parameter Conditions Ratings Unit Power source voltage –0.3 to 6.5 (Note 1) Input voltage –0.3 to V + 0.3...
  • Page 236 APPENDIX 3.1 Electrical characteristics (2) Recommended Operating Conditions (Extended operating temperature version) Table 3.1.14 Recommended operating conditions (1) = 2.4 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max. Power source voltage (ceramic) ) = 8 MHz (High-, Middle-speed mode) ) = 4 MHz (High-, Middle-speed mode) ) = 6 MHz (Double-speed mode)
  • Page 237 APPENDIX 3.1 Electrical characteristics Table 3.1.15 Recommended operating conditions (2) = 2.4 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max. “H” peak output current (Note 1) –P0 , P1 –P1 , P2 –P2...
  • Page 238 APPENDIX 3.1 Electrical characteristics (3) Electrical Characteristics (Extended operating temperature version) Table 3.1.16 Electrical characteristics (1) = 2.4 to 5.5 V, V = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min.
  • Page 239 APPENDIX 3.1 Electrical characteristics Table 3.1.17 Electrical characteristics (2) = 2.4 to 5.5 V, V = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Limits Symbol Test conditions Unit Min. Typ. Max. One Time PROM version High-speed mode, f(X ) = 8 MHz Output transistors “off”...
  • Page 240 APPENDIX 3.1 Electrical characteristics (4) A-D Converter Characteristics (Extended operating temperature version) Table 3.1.18 A-D Converter characteristics = 2.7 to 5.5 V, V = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min.
  • Page 241 APPENDIX 3.1 Electrical characteristics (5) Timing Requirements (Extended operating temperature version) Table 3.1.19 Timing requirements (1) = 4.0 to 5.5 V, V = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max.
  • Page 242 APPENDIX 3.1 Electrical characteristics (6) Switching Characteristics (Extended operating temperature version) Table 3.1.21 Switching characteristics (1) = 4.0 to 5.5 V, V = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max.
  • Page 243 APPENDIX 3.1 Electrical characteristics (CNTR (CNTR (CNTR CNTR 0.8V 0.2V (CNTR (CNTR (CNTR 0.8V CNTR 0.2V (CNTR (CNTR , INT 0.8V 0.2V (RESET) 0.8V RESET 0.2V 0.8V 0.2V CLK1 CLK1 CLK1 0.8V CLK1 0.2V (RxD -RxD CLK1 CLK1 0.8V (at receive) 0.2V -TxD CLK1...
  • Page 244 APPENDIX 3.1 Electrical characteristics 3.1.3 7540Group (Extended operating temperature 125 °C version) Applied to: M37540M2V-XXXFP/GP, M37540M4V-XXXFP/GP, M37540E8V-XXXFP/GP (1) Absolute Maximum Ratings (Extended operating temperature 125 °C version) Table 3.1.23 Absolute maximum ratings Symbol Parameter Conditions Ratings Unit Power source voltage –0.3 to 6.5 (Note 1) Input voltage –0.3 to V...
  • Page 245 APPENDIX 3.1 Electrical characteristics (2) Recommended Operating Conditions (Extended operating temperature 125 °C version) Table 3.1.24 Recommended operating conditions (1) = 2.4 to 5.5 V, Ta = –40 to 125 °C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max.
  • Page 246 APPENDIX 3.1 Electrical characteristics Table 3.1.25 Recommended operating conditions (2) = 2.4 to 5.5 V, Ta = –40 to 125 °C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max. “H” peak output current (Note 1) –P0 , P1 –P1 , P2 –P2...
  • Page 247 APPENDIX 3.1 Electrical characteristics (3) Electrical Characteristics (Extended operating temperature 125 °C version) Table 3.1.26 Electrical characteristics (1) = 2.4 to 5.5 V, V = 0 V, Ta = –40 to 125 °C, unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min.
  • Page 248 APPENDIX 3.1 Electrical characteristics Table 3.1.27 Electrical characteristics (2) = 2.4 to 5.5 V, V = 0 V, Ta = –40 to 125 °C, unless otherwise noted) Limits Symbol Test conditions Unit Min. Typ. Max. One Time PROM version High-speed mode, f(X ) = 8 MHz Output transistors “off”...
  • Page 249 APPENDIX 3.1 Electrical characteristics (4) A-D Converter Characteristics (Extended operating temperature 125 °C version) Table 3.1.28 A-D Converter characteristics = 2.7 to 5.5 V, V = 0 V, Ta = –40 to 125 °C, unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min.
  • Page 250 APPENDIX 3.1 Electrical characteristics (5) Timing Requirements (Extended operating temperature 125 °C version) Table 3.1.29 Timing requirements (1) = 4.0 to 5.5 V, V = 0 V, Ta = –40 to 125 °C, unless otherwise noted) Limits Symbol Parameter Unit Min.
  • Page 251 APPENDIX 3.1 Electrical characteristics (6) Switching Characteristics (Extended operating temperature 125 °C version) Table 3.1.30 Switching characteristics (1) = 4.0 to 5.5 V, V = 0 V, Ta = –40 to 125 °C, unless otherwise noted) Limits Symbol Parameter Unit Min.
  • Page 252 APPENDIX 3.1 Electrical characteristics (CNTR (CNTR (CNTR CNTR 0.8V 0.2V (CNTR (CNTR (CNTR 0.8V CNTR 0.2V (CNTR (CNTR , INT 0.8V 0.2V (RESET) 0.8V RESET 0.2V 0.8V 0.2V CLK1 CLK1 CLK1 0.8V CLK1 0.2V (RxD -RxD CLK1 CLK1 0.8V (at receive) 0.2V -TxD CLK1...
  • Page 253 APPENDIX 3.2 Typical characteristics 3.2 Typical characteristics Standard characteristics described below are just examples of the 7540 Group’s characteristics and are not guaranteed. For rated values, refer to “3.1 Electrical characteristics”. 3.2.1 Mask ROM version (1) Power source current characteristic example (V characteristics) Measuring condition: When system is operating in double-speed mode (A-D conversion not executed), Ta = 25 °C, Ceramic oscillation...
  • Page 254 APPENDIX 3.2 Typical characteristics Measuring condition: At WIT instruction execution (at wait), Ta = 25 °C, Ceramic oscillation ) = 8 MHz ) = 6 MHz ) = 4 MHz Power source voltage Vcc [V] Fig. 3.2.4 V characteristics (at WIT instruction execution: Mask ROM version) Measuring condition: At STP instruction execution (at stop), Ta = 25 °C, Ring oscillator stop Power source voltage Vcc [V] Fig.
  • Page 255 APPENDIX 3.2 Typical characteristics Measuring condition: A-D conversion executed/not executed (f(X ) = 8 MHz in high-speed mode), Ta = 25 °C, Ceramic oscillation During A-D conversion During not A-D conversion Power source voltage Vcc [V] Fig. 3.2.6 V characteristics (addition when operating A-D conversion, f(X ) = 8 MHz in high- speed mode: Mask ROM version) Measuring condition: A-D conversion executed/not executed (f(X...
  • Page 256 APPENDIX 3.2 Typical characteristics Measuring condition: When system is operating by ring oscillator (A-D conversion not executed), Ceramic oscillation stop Ta = –45 °C Ta = –25 °C Ta = 25 °C Ta = 90 °C Ta = 130 °C Power source voltage Vcc [V] Fig.
  • Page 257 APPENDIX 3.2 Typical characteristics (2) Power source current characteristic example (f(X characteristics) Measuring condition: When system is operating in double-speed mode (A-D conversion not executed), Ta = 25 °C, Ceramic oscillation = 5.0 V = 3.0 V Oscillation frequency f(X ) [MHz] Fig.
  • Page 258 APPENDIX 3.2 Typical characteristics Measuring condition: At WIT instruction execution, Ta = 25 °C, Ceramic oscillation = 5.0 V = 3.0 V Oscillation frequency f(X ) [MHz] Fig. 3.2.13 f(X characteristics (at WIT instruction execution: Mask ROM version) (3) Power source current characteristic example (Ta-I characteristics) Measuring condition: When system is operating by ring oscillator (A-D conversion not executed), Ceramic oscillation stop...
  • Page 259 APPENDIX 3.2 Typical characteristics (4) Port typical characteristic example (V characteristics) Measuring condition: V –V characteristics of I/O port (CMOS), V = 5.0 V, Ta = 25 °C (same characteristics pins: P0 –P0 , P1 , P2 –P2 , P3 –P3 Power source voltage Vcc [V] Fig.
  • Page 260 APPENDIX 3.2 Typical characteristics Measuring condition: V –V characteristics of RESET pin, V = 5.0 V, Ta = 25 °C “H” input voltage (V “L” input voltage (V Power source voltage Vcc [V] Fig. 3.2.18 V characteristics (RESET pin: Mask ROM version) Measuring condition: V –V characteristics of X...
  • Page 261 APPENDIX 3.2 Typical characteristics Measuring condition: V –HYS characteristics of RESET pin, V = 5.0 V, Ta = 25 °C Power source voltage Vcc [V] Fig. 3.2.21 V -HYS characteristics (RESET pin: Mask ROM version) Measuring condition: V –HYS characteristics of SIO pin, V = 5.0 V, Ta = 25 °C (same characteristics pins: RxD CLK1...
  • Page 262 APPENDIX 3.2 Typical characteristics (5) Port typical characteristic example (V characteristics) Measuring condition: V –I characteristics of P-channel (normal port), V = 3.0 V (same characteristics pins: P0 –P0 , P1 –P1 , P2 –P2 , P3 –P3 Ta = –40 °C Ta = 25 °C Ta = 125 °C “H”...
  • Page 263 APPENDIX 3.2 Typical characteristics (6) Port typical characteristic example (V characteristics) Measuring condition: V –I characteristics of N-channel (normal port), V = 3.0 V (same characteristics pins: P0 –P0 , P1 –P1 , P2 –P2 , P3 Ta = –40 °C Ta = 25 °C Ta = 125 °C “L”...
  • Page 264 APPENDIX 3.2 Typical characteristics Measuring condition: V –I characteristics of N-channel (LED drive port), V = 3.0 V (same characteristics pins: P3 –P3 Ta = –40 °C Ta = 25 °C Ta = 125 °C “L” output voltage V Fig. 3.2.28 V characteristics of N-channel (V = 3.0 V, LED drive port: Mask ROM version) Measuring condition: V...
  • Page 265 APPENDIX 3.2 Typical characteristics (7) Port typical characteristic example (V -IIL characteristics) Measuring condition: Port “L” input current when connecting pull-up transistor (same characteristics pins: P0 –P0 , P3 –P3 -0.4 Ta = –45 °C Ta = –25 °C -0.3 Ta = 25 °C Ta = 90 °C -0.2...
  • Page 266 APPENDIX 3.2 Typical characteristics (8) Port typical characteristic example (V -II(AD) characteristics) Measuring condition: f(X ) = 8 MHz in high-speed mode, V = 5.0 V, Ta = 25 °C (same characteristics pins: P2 –P2 -0.1 -0.2 -0.3 Input voltage V Fig.
  • Page 267 APPENDIX 3.2 Typical characteristics (9) Ring oscillator frequency typical characteristic example Measuring parameter: Ring oscillator frequency Ta = –45 °C Ta = –25 °C Ta = 25 °C Ta = 90 °C Ta = 130 °C Power source voltage Vcc [V] Fig.
  • Page 268 APPENDIX 3.2 Typical characteristics (10) RC oscillation frequency typical characteristic example Measuring parameter: RC oscillation frequency Measuring condition: V = 5.0 V, Ta = 25 °C, C = 33 pF External resistor R [kΩ] Fig. 3.2.36 R-f(X ) characteristics (RC oscillation frequency: Mask ROM version) Measuring parameter: RC oscillation frequency Measuring condition: V = 5.0 V, Ta = 25 °C, R = 6.8 kΩ...
  • Page 269 APPENDIX 3.2 Typical characteristics Measuring parameter: RC oscillation frequency ) ≅ 4 MHz (R = 5.1 kΩ, C = 20 pF) Measuring condition: Ta = 25 °C, f(X Power source voltage V Fig. 3.2.38 V -f(X ) characteristics (RC oscillation frequency: Mask ROM version) Measuring parameter: RC oscillation frequency ) ≅...
  • Page 270 APPENDIX 3.2 Typical characteristics (11) A-D conversion typical characteristics example Definition of A-D conversion accuracy The A-D conversion accuracy is defined below (refer to Fig. 3.2.40). Relative accuracy • Zero transition voltage (V This means an analog input voltage when the actual A-D conversion output data changes from “0”...
  • Page 271 APPENDIX 3.2 Typical characteristics A-D conversion accuracy typical characteristics-1 M37540M4-XXXFP A-D CONVERTER STEP WIDTH MEASUREMENT •V = 5.12 [V] •Zero transition voltage: 13.75 mV •V = 5.12 [V] •Full-scale transition voltage: 5120.94 mV •X = 4 [MHz] •Differential non-linearity error: –1.72 mV (–0.34 LSB) •Temp.
  • Page 272 APPENDIX 3.2 Typical characteristics A-D conversion accuracy typical characteristics-2 M37540M4-XXXFP A-D CONVERTER STEP WIDTH MEASUREMENT •V = 5.12 [V] •Zero transition voltage: 14.38 mV •V = 5.12 [V] •Full-scale transition voltage: 5121.88 mV •X = 6 [MHz] •Differential non-linearity error: 1.41 mV (0.28 LSB) •Temp.
  • Page 273 APPENDIX 3.2 Typical characteristics A-D conversion accuracy typical characteristics-3 M37540M4-XXXFP A-D CONVERTER STEP WIDTH MEASUREMENT •V = 5.12 [V] •Zero transition voltage: 30.31 mV •V = 5.12 [V] •Full-scale transition voltage: 5143.33 mV •X = 8 [MHz] •Differential non-linearity error: 1.72 mV (0.34 LSB) •Temp.
  • Page 274 APPENDIX 3.2 Typical characteristics 3.2.2 One Time PROM version (1) Power source current characteristic example (V characteristics) Measuring condition: When system is operating in double-speed mode (A-D conversion not executed), Ta = 25 °C, Ceramic oscillation ) = 6 MHz ) = 4 MHz ) = 2 MHz ) = 1 MHz...
  • Page 275 APPENDIX 3.2 Typical characteristics Measuring condition: At WIT instruction execution (at wait), Ta = 25 °C, Ceramic oscillation ) = 8 MHz ) = 6 MHz ) = 4 MHz Power source voltage Vcc [V] Fig. 3.2.47 V characteristics (at WIT instruction execution: One Time PROM version) Measuring condition: At STP instruction execution (at stop), Ta = 25 °C, Ring oscillator stop Power source voltage Vcc [V] Fig.
  • Page 276 APPENDIX 3.2 Typical characteristics Measuring condition: A-D conversion executed/not executed (f(X ) = 8 MHz in high-speed mode), Ta = 25 °C, Ceramic oscillation During A-D conversion During not A-D conversion Power source voltage Vcc [V] Fig. 3.2.49 V characteristics (addition when operating A-D conversion, f(X ) = 8 MHz in high- speed mode: One Time PROM version) Measuring condition: A-D conversion executed/not executed (f(X...
  • Page 277 APPENDIX 3.2 Typical characteristics Measuring condition: When system is operating by ring oscillator (A-D conversion not executed), Ceramic oscillation stop Ta = –45 °C Ta = –25 °C Ta = 25 °C Ta = 90 °C Ta = 130 °C Power source voltage Vcc [V] Fig.
  • Page 278 APPENDIX 3.2 Typical characteristics (2) Power source current characteristic example (f(X characteristics) Measuring condition: When system is operating in double-speed mode (A-D conversion not executed), Ta = 25 °C, Ceramic oscillation = 5.0 V = 3.0 V Oscillation frequency f(X ) [MHz] Fig.
  • Page 279 APPENDIX 3.2 Typical characteristics Measuring condition: At WIT instruction execution, Ta = 25 °C, Ceramic oscillation = 5.0 V = 3.0 V Oscillation frequency f(X ) [MHz] Fig. 3.2.56 f(X characteristics (at WIT instruction execution: One Time PROM version) (3) Power source current characteristic example (Ta-I characteristics) Measuring condition: When system is operating by ring oscillator (A-D conversion not executed), Ceramic oscillation stop...
  • Page 280 APPENDIX 3.2 Typical characteristics (4) Port typical characteristic example (V characteristics) Measuring condition: V –V characteristics of I/O port (CMOS), V = 5.0 V, Ta = 25 °C (same characteristics pins: P0 –P0 , P1 , P2 –P2 , P3 –P3 Power source voltage Vcc [V] Fig.
  • Page 281 APPENDIX 3.2 Typical characteristics Measuring condition: V –V characteristics of RESET pin, V = 5.0 V, Ta = 25 °C “H” input voltage (V “L” input voltage (V Power source voltage Vcc [V] Fig. 3.2.61 V characteristics (RESET pin: One Time PROM version) Measuring condition: V –V characteristics of X...
  • Page 282 APPENDIX 3.2 Typical characteristics Measuring condition: V –HYS characteristics of RESET pin, V = 5.0 V, Ta = 25 °C Power source voltage Vcc [V] Fig. 3.2.64 V -HYS characteristics (RESET pin: One Time PROM version) Measuring condition: V –HYS characteristics of SIO pin, V = 5.0 V, Ta = 25 °C (same characteristics pins: RxD CLK1...
  • Page 283 APPENDIX 3.2 Typical characteristics (5) Port typical characteristic example (V characteristics) Measuring condition: V –I characteristics of P-channel (normal port), V = 3.0 V (same characteristics pins: P0 –P0 , P1 –P1 , P2 –P2 , P3 –P3 Ta = 25 °C Ta = 125 °C “H”...
  • Page 284 APPENDIX 3.2 Typical characteristics (6) Port typical characteristic example (V characteristics) Measuring condition: V –I characteristics of N-channel (normal port), V = 3.0 V (same characteristics pins: P0 –P0 , P1 –P1 , P2 –P2 , P3 Ta = 25 °C Ta = 125 °C “L”...
  • Page 285 APPENDIX 3.2 Typical characteristics Measuring condition: V –I characteristics of N-channel (LED drive port), V = 3.0 V (same characteristics pins: P3 –P3 Ta = 25 °C Ta = 125 °C “L” output voltage V Fig. 3.2.71 V characteristics of N-channel (V = 3.0 V, LED drive port: One Time PROM version) Measuring condition: V –I...
  • Page 286 APPENDIX 3.2 Typical characteristics (7) Port typical characteristic example (V -IIL characteristics) Measuring condition: Port “L” input current when connecting pull-up transistor (same characteristics pins: P0 –P0 , P3 –P3 -0.5 Ta = –45 °C Ta = –25 °C -0.4 Ta = 25 °C -0.3 Ta = 90 °C...
  • Page 287 APPENDIX 3.2 Typical characteristics (8) Port typical characteristic example (V -II(AD) characteristics) Measuring condition: f(X ) = 8 MHz in high-speed mode, V = 5.0 V, Ta = 25 °C (same characteristics pins: P2 –P2 -0.1 -0.2 -0.3 Input voltage V Fig.
  • Page 288 APPENDIX 3.2 Typical characteristics (9) Ring oscillator frequency typical characteristic example Measuring parameter: Ring oscillator frequency Ta = –45 °C Ta = –25 °C Ta = 25 °C Ta = 90 °C Ta = 130 °C Power source voltage Vcc [V] Fig.
  • Page 289 APPENDIX 3.2 Typical characteristics (10) RC oscillation frequency typical characteristic example Measuring parameter: RC oscillation frequency Measuring condition: V = 5.0 V, Ta = 25 °C C = 20 pF C = 33 pF C = 47 pF External resistor R [kΩ] Fig.
  • Page 290 APPENDIX 3.2 Typical characteristics Measuring parameter: RC oscillation frequency Measuring condition: Ta = 25 °C, R = 5.1 kΩ/C = 33 pF Power source voltage V Fig. 3.2.81 V -f(X ) characteristics (RC oscillation frequency: One Time PROM version) Measuring parameter: RC oscillation frequency Measuring condition: R = 5.1 kΩ, C = 33 pF = 5.0 V = 3.0 V...
  • Page 291 APPENDIX 3.2 Typical characteristics (11) A-D conversion typical characteristics example Definition of A-D conversion accuracy The A-D conversion accuracy is defined below (refer to Fig. 3.2.83). Relative accuracy • Zero transition voltage (V This means an analog input voltage when the actual A-D conversion output data changes from “0”...
  • Page 292 APPENDIX 3.2 Typical characteristics A-D conversion accuracy typical characteristics-1 M37540E8FP A-D CONVERTER STEP WIDTH MEASUREMENT •V = 5.12 [V] •Zero transition voltage: 6.88 mV •V = 5.12 [V] •Full-scale transition voltage: 5115.63 mV •X = 4 [MHz] •Differential non-linearity error: –2.34 mV (–0.47 LSB) •Temp.
  • Page 293 APPENDIX 3.2 Typical characteristics A-D conversion accuracy typical characteristics-2 M37540E8FP A-D CONVERTER STEP WIDTH MEASUREMENT •V = 5.12 [V] •Zero transition voltage: 5.94 mV •V = 5.12 [V] •Full-scale transition voltage: 5113.44 mV •X = 6 [MHz] •Differential non-linearity error: 3.28 mV (0.66 LSB) •Temp.
  • Page 294 APPENDIX 3.2 Typical characteristics A-D conversion accuracy typical characteristics-3 M37540E8FP A-D CONVERTER STEP WIDTH MEASUREMENT •V = 5.12 [V] •Zero transition voltage: 5.63 mV •V = 5.12 [V] •Full-scale transition voltage: 5115.31 mV •X = 8 [MHz] •Differential non-linearity error: –2.66 mV (–0.53 LSB) •Temp.
  • Page 295 APPENDIX 3.3 Notes on use 3.3 Notes on use 3.3.1 Notes on input and output ports Notes on using input and output ports are described below. (1) Notes in stand-by state In stand-by state* for low-power dissipation, do not make input levels of an input port and an I/O port “undefined”.
  • Page 296 APPENDIX 3.3 Notes on use 3.3.2 Termination of unused pins (1) Terminate unused pins I/O ports : • Set the I/O ports for the input mode and connect them to V or V through each resistor of 1 kΩ to 10 kΩ. Ports that permit the selecting of a built-in pull-up resistor can also use this resistor.
  • Page 297 APPENDIX 3.3 Notes on use 3.3.3 Notes on Timer • When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1). • When a count source of timer X, timer Y or timer Z is switched, stop a count of timer X. 3.3.4 Notes on Timer A Notes on using timer A are described below.
  • Page 298 APPENDIX 3.3 Notes on use 3.3.6 Notes on Timer X Notes on using each mode of timer X are described below. (1) Count source ) can be used only when a ceramic oscillator or a ring oscillator is used. Do not use f(X ) at RC oscillation.
  • Page 299 APPENDIX 3.3 Notes on use 3.3.7 Notes on timer Y and timer Z Notes on using each mode of Timer Y and Timer Z are described below. (1) Timer mode (timer Y and timer Z) In the timer mode, TYP and TYS is not used. (2) Programmable waveform generation mode (timer Y and timer Z) In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid by writing to TYP because the setting to them is executed all at once by writing to TYP.
  • Page 300 APPENDIX 3.3 Notes on use The waveform extension function by the timer Z waveform extension control bits can be used only when “00 ” is set to Prescaler Z. When the value other than “00 ” is set to Prescaler Z, be sure to set “0” to EXPZP. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used.
  • Page 301 APPENDIX 3.3 Notes on use (5) Common to all modes (timer Y and timer Z) Timer Y can stop counting by setting “1” to the timer Y count stop bit in any mode. Also, when Timer Y underflows, the timer Y interrupt request bit is set to “1”. Timer Y reloads the value of latch when counting is stopped by the timer Y count stop bit.
  • Page 302 APPENDIX 3.3 Notes on use (2) Notes when selecting UART When the clock asynchronous serial I/O1 (UART) is used, serial I/O2 can be used only when BRG output divided by 16 is selected as the synchronous clock. When the transmit operation is stopped, clear the transmit enable bit to “0” (transmit disabled). Reason Same as (1) When the receive operation is stopped, clear the receive enable bit to “0”...
  • Page 303 APPENDIX 3.3 Notes on use 3.3.9 Notes on serial I/O2 Notes on using serial I/O2 are described below. (1) Note on serial I/O1 Serial I/O2 can be used only when serial I/O1 is not used or serial I/O1 is used as UART and the BRG output divided by 16 is selected as the synchronous clock.
  • Page 304 APPENDIX 3.3 Notes on use 3.3.10 Notes on A-D converter Notes on A-D converter are described below. (1) Analog input pin Figure 3.3.2 shows the internal equivalent circuit of an analog input. In order to execute the A-D conversion correctly, to complete the charge to an internal capacitor within the specified time is required.
  • Page 305 APPENDIX 3.3 Notes on use 3.3.11 Notes on oscillation stop detection circuit Notes on using oscillation stop detection circuit are described below. (1) Note on ring oscillator The 7540 Group starts operation by the ring oscillator. (2) Notes on oscillation circuit stop detection circuit When the stop mode is used, set the oscillation stop detection function to “invalid”.
  • Page 306 APPENDIX 3.3 Notes on use When the ring oscillation is used as the operation clock, the CPU clock division ratio is the middle- speed mode. When the state transition state 2→state 3→state 4 is performed, execute the NOP instruction as shown below according to the division ratio of CPU clock.
  • Page 307 APPENDIX 3.3 Notes on use 3.3.12 Notes on CPU mode register (1) Switching method of CPU mode register after releasing reset Switch the CPU mode register (CPUM) at the head of program after releasing reset in the following method. After releasing reset Start with a built-in ring oscillator ( Note) An initial value is set as a ceramic Switch the oscillation mode...
  • Page 308 APPENDIX 3.3 Notes on use 3.3.13 Notes on interrupts (1) Switching external interrupt detection edge For the products able to switch the external interrupt detection edge, switch it as the following sequence. Clear an interrupt enable bit to “0” (interrupt disabled) ↓...
  • Page 309 APPENDIX 3.3 Notes on use (3) Structure of interrupt control register 2 Fix the bit 7 of the interrupt control register 1 to “0”. Figure 3.3.7 shows the structure of the interrupt control register 2. Interrupt control register 2 (address: 003F Interrupt enable bit Not used (fix this bit to “0”) Fig.
  • Page 310 APPENDIX 3.3 Notes on use 3.3.15 Notes on programming (1) Processor status register Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations.
  • Page 311 APPENDIX 3.3 Notes on use (2) Decimal calculations Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal notation, set the decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction, execute another instruction before executing the SEC, CLC, or CLD instruction.
  • Page 312 APPENDIX 3.3 Notes on use (7) Instruction Execution Timing The instruction execution time can be obtained by multiplying the frequency of the internal clock f by the number of cycles mentioned in the machine-language instruction table. The frequency of the internal clock f is the same as that of the X in double-speed mode, twice the cycle in high-speed mode and 8 times the X cycle in middle-speed mode.
  • Page 313 APPENDIX 3.3 Notes on use 3.3.18 Notes on built-in PROM version (1) Programming adapter Use a special programming adapter shown in Table 3.3.1 and a general-purpose PROM programmer when reading from or programming to the built-in PROM in the built-in PROM version. Table 3.3.1 Programming adapters Programming adapter Microcomputer...
  • Page 314 APPENDIX 3.4 Countermeasures against noise 3.4 Countermeasures against noise 3.4.1 Shortest wiring length (1) Package Select the smallest possible package to make the total wiring length short. Reason The wiring length depends on a microcomputer package. Use of a small package, for example QFP and not DIP, makes the total wiring length short to reduce influence of noise.
  • Page 315 APPENDIX 3.4 Countermeasures against noise (3) Wiring for clock input/output pins • Make the length of wiring which is connected to clock I/O pins as short as possible. • Make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an oscillator and the V pin of a microcomputer as short as possible.
  • Page 316 APPENDIX 3.4 Countermeasures against noise (5) Wiring to V pin of One Time PROM version Connect an approximately 5 kΩ resistor to the V pin the shortest possible in series and also to the pin. When not connecting the resistor, make the length of wiring between the V pin and the pin the shortest possible.
  • Page 317 APPENDIX 3.4 Countermeasures against noise 3.4.3 Wiring to analog input pins • Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. •...
  • Page 318 APPENDIX 3.4 Countermeasures against noise (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise.
  • Page 319 APPENDIX 3.4 Countermeasures against noise 3.4.6 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer.
  • Page 320 APPENDIX 3.5 List of registers 3.5 List of registers Port Pi b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (Pi) (i = 0, 2, 3) [Address : 00 , 04 , 06 Name Function At reset Port Pi In output mode Write Port latch...
  • Page 321 APPENDIX 3.5 List of registers Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i = 0, 2, 3) [Address : 01 , 05 , 07 Name Function At reset 0 : Port Pi input mode Port Pi direction register 1 : Port Pi...
  • Page 322 APPENDIX 3.5 List of registers Pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Pull-up control register (PULL) [Address : 16 Name Function At reset 0 : Pull-up Off pull-up control bit 1 : Pull-up On 0 : Pull-up Off pull-up control bit 1 : Pull-up On 0 : Pull-up Off...
  • Page 323 APPENDIX 3.5 List of registers Transmit/Receive buffer register b7 b6 b5 b4 b3 b2 b1 b0 Transmit/Receive buffer register (TB/RB) [Address : 18 Function At reset The transmission data is written to or the receive data is read out from this buffer register. •...
  • Page 324 APPENDIX 3.5 List of registers Serial I/O1 control register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O1 control register (SIO1CON) [Address : 1A Function Name At reset BRG count source 0 : f(X 1 : f(X selection bit (CSS) When clock synchronous serial I/O Serial I/O1 synchronous clock selection bit (SCS)
  • Page 325 APPENDIX 3.5 List of registers Baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 Baud rate generator (BRG) [Address : 1C Function At reset Set a count value of baud rate generator. Fig. 3.5.11 Structure of Baud rate generator 7540 Group User’s Manual 3-103...
  • Page 326 APPENDIX 3.5 List of registers Timer A mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer A mode register (TAM) [Address : 1D Function Name At reset Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0”.
  • Page 327 APPENDIX 3.5 List of registers Timer A register (low-order, high-order) b7 b6 b5 b4 b3 b2 b1 b0 Timer A register (low-order, high-order) (TAL, TAH) [Address : 1E , 1F Function At reset •Set a count value of timer A. •The value set in this register is written to both timer A and timer A latch at the same time.
  • Page 328 APPENDIX 3.5 List of registers Prescaler Y, Prescaler Z b7 b6 b5 b4 b3 b2 b1 b0 Prescaler Y (PREY) [Address : 21 Prescaler Z (PREZ) [Address : 25 Function At reset •Set a count value of each prescaler. •The value set in this register is written to both each prescaler and the corresponding prescaler latch at the same time.
  • Page 329 APPENDIX 3.5 List of registers Timer Y primary, Timer Z primary b7 b6 b5 b4 b3 b2 b1 b0 Timer Y primary, Timer Z primary (TYP, TZP) [Address : 23 , 27 Function At reset •Set a count value of the corresponding timer. •When the corresponding timer is stopped, the value set in this register is written to both the corresponding primary latch and the corresponding timer at the same time.
  • Page 330 APPENDIX 3.5 List of registers Prescaler 1 b7 b6 b5 b4 b3 b2 b1 b0 Prescaler 1 (PRE1) [Address : 28 Function At reset •Set a count value of prescaler 1. •The value set in this register is written to both prescaler 1 and the prescaler 1 latch at the same time.
  • Page 331 APPENDIX 3.5 List of registers One-shot start register b7 b6 b5 b4 b3 b2 b1 b0 One-shot start register (ONS) [Address : 2A Function Name At reset 0 : One-shot stop Timer Z one-shot start bit 1 : One-shot start Nothing is allocated for these bits.
  • Page 332 APPENDIX 3.5 List of registers Timer X mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register (TXM) [Address : 2B Function At reset Name b1 b0 Timer X operating mode bits 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement...
  • Page 333 APPENDIX 3.5 List of registers Prescaler X b7 b6 b5 b4 b3 b2 b1 b0 Prescaler X (PREX) [Address : 2C Function At reset •Set a count value of prescaler X. •The value set in this register is written to both prescaler X and the prescaler X latch at the same time.
  • Page 334 APPENDIX 3.5 List of registers Timer count source set register b7 b6 b5 b4 b3 b2 b1 b0 Timer count source set register (TCSS) [Address : 2E Function Name At reset Timer X count source b1 b0 0 0 : f(X )/16 selection bits 0 1 : f(X...
  • Page 335 APPENDIX 3.5 List of registers S e r i a l I / O 2 c o n t r o l r e g i s t e r b 7 b 6 b5 b 4 b 3 b 2 b 1 b 0 S e r i a l I / O 2 c o n t r o l r e g i s t e r ( S I O 2 C O N ) [ A d d r e s s : 3 0 Function N a m e...
  • Page 336 APPENDIX 3.5 List of registers A-D control register b7 b6 b5 b4 b3 b2 b1 b0 A-D control register (ADCON) [Address : 34 Function At reset Name Analog input pin selection bits b2 b1 b0 0 0 0 : P2 0 0 1 : P2 0 1 0 : P2 0 1 1 : P2...
  • Page 337 APPENDIX 3.5 List of registers A-D conversion register (high-order) b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion register (high-order) (ADH) [Address : 36 Function At reset The read-only register in which the A-D conversion’s results are stored. < 10-bit read> Nothing is allocated for these bits.
  • Page 338 APPENDIX 3.5 List of registers Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer control register (WDTCON) [Address : 39 Name Function At reset Watchdog timer H (The high-order 6 bits are read-only bits.) 0 : STP instruction enabled STP instruction disable bit 1 : STP instruction disabled Watchdog timer H count...
  • Page 339 APPENDIX 3.5 List of registers CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) [Address : 3B Function Name At reset b1 b0 Processor mode bits ( Note 1) 0 0 : Single-chip mode 0 1 : Not available 1 0 : Not available 1 1 : Not available...
  • Page 340 APPENDIX 3.5 List of registers Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address : 3C Function Name At reset Serial I/O1 receive 0 : No interrupt request issued 1 : Interrupt request issued interrupt request bit 0 : No interrupt request issued Serial I/O1 transmit interrupt...
  • Page 341 APPENDIX 3.5 List of registers Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E Function Name At reset Serial I/O1 receive 0 : Interrupt disabled 1 : Interrupt enabled interrupt enable bit 0 : Interrupt disabled Serial I/O1 transmit interrupt...
  • Page 342 APPENDIX 3.6 Package outline 3.6 Package outline 32P4B Plastic 32pin 400mil SDIP EIAJ Package Code JEDEC Code Weight(g) Lead Material SDIP32-P-400-1.78 – Alloy 42/Cu Alloy Dimension in Millimeters Symbol – – 5.08 0.51 – – – – 0.35 0.45 0.55 0.63 0.73 1.03...
  • Page 343 APPENDIX 3.6 Package outline 36P2R-A Plastic 36pin 450mil SSOP EIAJ Package Code JEDEC Code Weight(g) Lead Material SSOP36-P-450-0.80 – 0.53 Alloy 42 Recommended Mount Pad Dimension in Millimeters Symbol – – – – – – – – – .765 – –...
  • Page 344 APPENDIX 3.7 Machine instructions 3.7 Machine instructions Addressing mode Symbol Function Details BIT, A, R BIT, A BIT, ZP, R BIT, ZP OP n OP n # OP n # OP n # OP n # OP n When T = 0 When T = 0, this instruction adds the contents 69 2 65 3...
  • Page 345 APPENDIX 3.7 Machine instructions Addressing mode Processor status register ZP, X ZP, Y ABS, X ABS, Y ZP, IND IND, X IND, Y OP n # OP n # OP n # OP n # OP n # OP n # OP n OP n OP n...
  • Page 346 APPENDIX 3.7 Machine instructions Addressing mode Symbol Function Details BIT, A BIT, ZP OP n OP n # OP n # OP n # OP n # OP n N = 0? This instruction takes a branch to the ap- (Note 4) pointed address if N is 0.
  • Page 347 APPENDIX 3.7 Machine instructions Addressing mode Processor status register ZP, X ZP, Y ABS, X ABS, Y ZP, IND IND, X IND, Y OP n # OP n # OP n # OP n # OP n # OP n # OP n OP n OP n...
  • Page 348 APPENDIX 3.7 Machine instructions Addressing mode Symbol Function Details BIT, A BIT, ZP OP n OP n # OP n # OP n # OP n # OP n X ← X – 1 This instruction subtracts one from the current contents of X.
  • Page 349 APPENDIX 3.7 Machine instructions Addressing mode Processor status register ZP, X ZP, Y ABS, X ABS, Y ZP, IND IND, X IND, Y OP n # OP n # OP n # OP n # OP n # OP n # OP n OP n OP n...
  • Page 350 APPENDIX 3.7 Machine instructions Addressing mode Symbol Function Details BIT, A BIT, ZP OP n OP n # OP n # OP n # OP n # OP n This instruction shifts either A or M one bit to 4A 2 0 →...
  • Page 351 APPENDIX 3.7 Machine instructions Addressing mode Processor status register ZP, X ZP, Y ABS, X ABS, Y ZP, IND IND, X IND, Y OP n # OP n # OP n # OP n # OP n # OP n # OP n OP n OP n...
  • Page 352 APPENDIX 3.7 Machine instructions Addressing mode Symbol Function Details BIT, A BIT, ZP OP n OP n # OP n # OP n # OP n # OP n E9 2 E5 3 When T = 0 When T = 0, this instruction subtracts the A ←...
  • Page 353 APPENDIX 3.7 Machine instructions Addressing mode Processor status register ZP, X ZP, Y ABS, X ABS, Y ZP, IND IND, X IND, Y OP n # OP n # OP n # OP n # OP n # OP n # OP n OP n OP n...
  • Page 354 APPENDIX 3.7 Machine instructions Symbol Contents Symbol Contents Implied addressing mode Addition Immediate addressing mode – Subtraction Accumulator or Accumulator addressing mode Multiplication BIT, A Accumulator bit addressing mode Division BIT, A, R Accumulator bit relative addressing mode Logical OR Zero page addressing mode Logical AND V –...
  • Page 355 APPENDIX 3.8 List of instruction code 3.8 List of instruction code – D 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Hexadecimal – D notation — — 0000 IND, X ZP, IND 0, A 0, ZP 0, A...
  • Page 356 APPENDIX 3.9 SFR memory map 3.9 SFR memory map Port P0 (P0) Timer Y, Z mode register (TYZM) 0000 0020 Port P0 direction register (P0D) Prescaler Y (PREY) 0001 0021 Port P1 (P1) Timer Y secondary (TYS) 0002 0022 Port P1 direction register (P1D) Timer Y primary (TYP) 0003 0023...
  • Page 357 APPENDIX 3.10 Pin configurations 3.10 Pin configurations (Top view) (LED M37540Mx-XXXGP (LED M37540MxT-XXXGP (LED M37540MxV-XXXGP (LED CLK1 CLK2 M37540ExGP (LED RDY1 DATA2 M37540E8T-XXXGP /CNTR M37540E8V-XXXGP Package type: 32P6U-A Fig. 3.10.1 32P6U-A package pin configuration 7540 Group User’s Manual 3-135...
  • Page 358 APPENDIX 3.10 Pin configurations (Top view) CLK1 CLK2 RDY1 DATA2 /CNTR /CNTR /INT (LED )/INT (LED RESET (LED (LED (LED (LED (LED Package type: 36P2R-A Fig. 3.10.2 36P2R-A package pin configuration 3-136 7540 Group User’s Manual...
  • Page 359 APPENDIX 3.10 Pin configurations (Top view) CLK1 CLK2 RDY1 DATA2 /CNTR /CNTR /INT RESET (LED (LED (LED (LED (LED Package type: 32P4B Fig. 3.10.3 32P4B package pin configuration 7540 Group User’s Manual 3-137...
  • Page 360 APPENDIX 3.10 Pin configurations (Top view) /CNTR RDY1 DATA2 CLK1 CLK2 /CNTR /INT (LED )/INT (LED RESET (LED (LED (LED (LED (LED Outline 42S1M Fig. 3.10.4 42S1M package pin configuration 3-138 7540 Group User’s Manual...
  • Page 361 APPENDIX 3.11 Differences between 7540 Group and 7531 Group 3.11 Differences between 7540 Group and 7531 Group Table 3.11.1 shows the differences between 7540 Group and 7531 Group. Table 3.11.1 Differences between 7540 Group and 7531 Group (Performance overview) Parameter 7540 Group 7531 Group Number of basic instructions...
  • Page 362 APPENDIX 3.11 Differences between 7540 Group and 7531 Group Figure 3.11.1 shows the memory map of 7540 Group and 7531 Group. 7 5 3 1 G r o u p 7 5 4 0 G r o u p 0000 0 0 0 0 S F R a r e a SFR area...
  • Page 363 APPENDIX 3.11 Differences between 7540 Group and 7531 Group Figure 3.11.2 shows the memory map of interrupt vector area of 7540 Group and 7531 Group. FFDC B R K i n s t r u c t i o n i n t e r r u p t FFDD FFDE Reserved area...
  • Page 364 APPENDIX 3.11 Differences between 7540 Group and 7531 Group Figure 3.11.3 shows the timer function of 7540 Group and 7531 Group. 7 5 3 1 G r o u p 7540 Group T i m e r 1 ( 8 - b i t t i m e r ) T i m e r 1 ( 8 - b i t t i m e r ) •...
  • Page 365 Editioned by Committee of editing of Mitsubishi Semiconductor USER’S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©2002 MITSUBISHI ELECTRIC CORPORATION...
  • Page 366 User’s Manual 7540 Group MITSUBISHI ELECTRIC CORPORATION HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN New publication, effective Sep. 2002 © 2002 MITSUBISHI ELECTRIC CORPORATION. Specifications subject to change without notice.

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