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Alpha Data ADM-XA210 User Manual

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ADM-XA210
User Manual
Document Revision: 1.0
Mar 4, 2025

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Summary of Contents for Alpha Data ADM-XA210

  • Page 1 ADM-XA210 User Manual Document Revision: 1.0 Mar 4, 2025...
  • Page 2 ADM-XA210 User Manual V1.0 - Mar 4, 2025 © 2025 Copyright Alpha Data Parallel Systems Ltd. All rights reserved. This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Ltd.

  • Page 3: Table Of Contents

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 Table Of Contents Introduction ............................1 Key Features ..........................1 References & Specifications ......................3 Installation ............................4 Hardware Installation ........................4 2.1.1 Handling Instructions ......................... 4 2.1.2 Motherboard / Carrier Requirements ..................4 2.1.3...
  • Page 4 XRM Connector CN1, Field 3 ......................37 Table 27 XRM Connector CN2 ........................38 Table 28 Full Pin Map ............................. 39 List of Figures Figure 1 ADM-XA210 Block Diagram ....................... 2 Figure 2 Alpha Data Power Estimator Spreadsheet ..................5...
  • Page 5 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Figure 3 ADM-XRC-9R1B Vivado Example Design ..................6 Figure 4 LED Locations ............................ 8 Figure 5 MRSTO Circuit ..........................11 Figure 6 JTAG Header U42 ..........................12 Figure 7 JTAG Boundary Scan Chain ......................12 Figure 8 Board Clock Diagram ........................
  • Page 6 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Page Intentionally left blank...

  • Page 7: Introduction

    V1.0 - Mar 4, 2025 1 Introduction The ADM-XA210 is a high-performance XMC for applications using the Versal from AMD. The ADM-XA210 is available in air-cooled and conduction-cooled configurations. View the Ordering Info tab at ADM-XA210 Product Page www.alpha-data.com ...

  • Page 8: Figure 1 Adm-Xa210 Block Diagram

    COM0 GTY[7:7] RS232 CAN PHY GTY[6:0] (x8) USB 2.0 USB PHY GPIO 1000-BaseT Ethernet (x8) JTAG/UART USB 2.0 System Monitor Microcontroller LPDDR5 4 Banks Supply Monitoring Power supply GTY [7:0] Figure 1 : ADM-XA210 Block Diagram Page 2 Introduction ad-ug-1506_v1_0.pdf...

  • Page 9: References & Specifications

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 1.2 References & Specifications ANSI/VITA 42.0 XMC Standard, December 2008, VITA, ISBN 1-885731-49-3 ANSI/VITA 42.2 XMC Serial RapidIO Protocol Layer Standard, Feb 2006, VITA, ISBN 1-885731-41-8 ANSI/VITA 42.3 XMC PCI Express Protocol Layer Standard, June 2006, VITA, ISBN 1-885731-43-4 PMC/XMC Rear I/O Fabric Signal Mapping on 3U and 6U VPX Modules Standard, ANSI/VITA 46.9...

  • Page 10: Installation

    - Store in ESD safe bag. 2.1.2 Motherboard / Carrier Requirements The ADM-XA210 is a single-width XMC.3 mezzanine card equipped with P6 and P4 connectors. The motherboard or carrier must comply with the XMC.3 (VITA 42.3) specification for the Primary XMC connector, J5.

  • Page 11: Cooling Requirements

    The power dissipation of the board is highly dependent on the FPGA application. A power estimator spreadsheet is available on request from Alpha Data. This should be used in conjunction with AMD power estimation tools to determine the exact current requirements for each power rail.

  • Page 12: Mechanical

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 3 Mechanical Parameter Condition Value Length 149.0mm Length 143.75mm Width 74.0mm Weight No Heatsink 74.0mm Weight AC Assembly TBD g Weight CC Assembly TBD g Table 2 : Mechanical Info 4 Example Design An FPGA and CPIS ARM/Linux example design is available, contact support@alpha-data.com for access.

  • Page 13: Functional Description

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 5 Functional Description 5.1 Overview 5.1.1 Switch Definitions There are two sets of eight DIP switches (16 switches in total) placed on the rear of the board. Some switch states can be controlled using the FPGA or the AVR system monitor. These signals are shown in the corresponding table.

  • Page 14: Led Definitions

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 5.1.2 LED Definitions Figure 4 : LED Locations Comp. Ref. Function ON State OFF State D1 (Red) PS ERROR PS ERROR PS OK D2 (Green) PS_DONE FPGA Configured FPGA Not configured D22 (Green)

  • Page 15: Xrm Interface And Front-Panel I/O

    The XRM interface provides a high-performance and flexible front-panel interface through a range of interchangeable XRM modules. Further details of the XRM modules can be found on the Alpha Data website. The XRM interface consists of two Samtec connectors, CN1 and CN2.

  • Page 16: Xrm I/F - High-Speed Serial Links

    5.2.5 XRM IO Voltage Override Each XRM is built with an I2C EEPROM that contains vital product information (VPD) such as part number, serial number, operating voltage, and product-specific information. For designing custom XRMs, contact Alpha Data for details on duplicating this VPD data.

  • Page 17: Xmc Platform Interface

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 5.3 XMC Platform Interface 5.3.1 IPMI I2C A 2 Kbit I2C EEPROM (type M24C02) is connected to the XMC IPMI. This memory contains board information (type, voltage requirements etc.) as defined in the XMC base specification.

  • Page 18: Jtag Interface

    A JTAG boundary scan chain is connected to header U42. This allows the connection of an AMD JTAG cable for FPGA debug using the AMD tools. The ADM-XA210 comes with an adaptor board that attach to this connector, providing access to a standard 14-pin JTAG header that is compatible with the AMD Platform II JTAG box. The adaptor board connects through holes at the rear of the PCBm enabling JTAG accessed while the board is mounted to a carrier.

  • Page 19: Xmc Jtag Interface

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 5.4.2 XMC JTAG Interface When the JTAG interface on the XMC connector is unused, XMC_TDI connected directly to XMC_TDO to loop back the JTAG chain. The XMC_JTAG interface can be connected to the on-board JTAG interface (through level-translators) by switching SW1-5 ON.

  • Page 20: Clocks

    V1.0 - Mar 4, 2025 5.5 Clocks The ADM-XA210 provides a wide variety of clocking options, using some fixed oscillators and a user-programmable clock generator. These clocks can be combined with the FPGA's internal PLLs to suit a wide variety of communication protocols.

  • Page 21: 300 Mhz Reference Clocks (Mem_Clk And Fabric_Clk)

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 5.5.1 300 MHz Reference Clocks (MEM_CLK and FABRIC_CLK) The fixed 300 MHz reference clocks, MEM_CLK and FABRIC_CLK, are differential LVDS signals. MEM_CLK0 and MEM_CLK1 are used as the input clocks for the LPDDR4 SDRAM interfaces.

  • Page 22: Fixed Oscillators

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 5.5.5 Fixed Oscillators There are five fixed oscillators on the board for the digital system. The USB and Ethernet reference clocks are used internally by the PHYs. Signal Frequency FPGA pin PS Ref Clock 33.3333MHz...

  • Page 23: Ps Block

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 5.6 PS Block 5.6.1 Boot Modes BootMode0 BootMode1 BootMode2 Boot Mode (SW2-1) (SW2-2) (SW2-3) JTAG Quad SPI SD Flash Reserved Table 12 : Boot Mode Selection 5.6.2 Quad SPI Flash Memory 1 Gb Flash Memory (2x Micron MT25QU512AB) is used for storing executable code and data for the PS and PL, such as a bootloader, operating system and bitstream.

  • Page 24: Ethernet Interfaces

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 5.6.4 Ethernet Interfaces The XA210 has one 1000BASE-T Ethernet interface at the rear connector P4. The interface uses a Marvell 88E1512 PHY, connected to the PS via RGMII. 1000Base-T RGMII ETH0 Magnetics...

  • Page 25: Usb Interfaces

    V1.0 - Mar 4, 2025 5.6.6 USB Interfaces The ADM-XA210 has two external USB interfaces connected to the rear connector P4. The PS is configured as the USB host for these external interfaces. The on-board system monitor is accessible from the micro-USB connector.

  • Page 26: Interfaces

    The FPGA IO is arranged in banks, each with its own power supply pins. The bank numbers, their voltage and function are shown in FPGA IO Banks. Full details of the IOSTANDARD required for each signal are given in the constraint files of ADM-XA210 example designs. IO Banks Voltage Purpose 3.3V...

  • Page 27: Gpio

    Figure 13 : GPIO Block Diagram 5.7.4 Memory Interfaces The ADM-XA210 has two independent banks of LPDDR4 SDRAM. Each bank consists of two 32-bit wide memory devices, each device made up of two 16-bit channels, capable of running at up to 2133MHz (DDR-4266) .

  • Page 28: Configuration

    Monitoring. 5.9 System Monitoring The ADM-XA210 has the ability to monitor temperature and voltage to maintain a check on the operation of the board. This monitoring is implemented using the Atmel AVR microcontroller. Control algorithms within the microcontroller automatically check line voltages and onboard temperatures and share the information with the PL.

  • Page 29: Automatic Temperature Monitoring

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 5.9.1 Automatic Temperature Monitoring The onboard system monitor microcontroller contains pre-programmed temperature limits. These limits are shown in Temperature Limits: Target FPGA Board Commercial 0 degC +85 degC 0 degC +85 degC...

  • Page 30: System Monitor Interfaces

    ADM-XA210. One is through the USB-C connector (as shown in Interfaces). This communication interface is intended to be used with Alpha Data utility called avr2util. Avr2util can be run from the command line from a host PC connected to the board.

  • Page 31: Appendix A: Rear Connector Pinouts

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 Appendix A: Rear Connector Pinouts Appendix A.1: Primary XMC Connector, P5 PET_P0 PET_N0 PET_P1 PET_N1 VPWR MRSTI_L PET_P2 PET_N2 PET_P3 PET_N3 VPWR MRSTO_L PET_P4 PET_N4 PET_P5 PET_N5 VPWR 12V0 PET_P6 PET_N6 PET_P7...

  • Page 32: Table 19 Pn5 Hssio Pinout

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin FPGA Bank P5_PCIE_TX_PIN_P0 AB38 P5_PCIE_TX_PIN_N0 AB39 P5_PCIE_RX_PIN_P0 AC41 P5_PCIE_RX_PIN_N0 AC42 P5_PCIE_TX_PIN_P1 AA36 P5_PCIE_TX_PIN_N1 AA37 P5_PCIE_RX_PIN_P1 AA41 P5_PCIE_RX_PIN_N1 AA42 P5_PCIE_TX_PIN_P2 P5_PCIE_TX_PIN_N2 P5_PCIE_RX_PIN_P2 P5_PCIE_RX_PIN_N2 P5_PCIE_TX_PIN_P3 P5_PCIE_TX_PIN_N3 P5_PCIE_RX_PIN_P3 P5_PCIE_RX_PIN_N3 P5_PCIE_TX_PIN_P4 P5_PCIE_TX_PIN_N4 P5_PCIE_RX_PIN_P4...

  • Page 33: Secondary Xmc Connector, P6

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 Appendix A.2: Secondary XMC Connector, P6 PN6_TX_P0 PN6_TX_N0 GPIO_37 PN6_TX_P1 PN6_TX_N1 GPIO_38 GPIO_35 GPIO_36 PN6_TX_P2 PN6_TX_N2 GPIO_33 PN6_TX_P3 PN6_TX_N3 GPIO_34 GPIO_31 GPIO_32 PN6_TX_P4 PN6_TX_N4 GPIO_29 PN6_TX_P5 PN6_TX_N5 GPIO_30 GPIO_27 GPIO_28 PN6_TX_P6 PN6_TX_N6...

  • Page 34: Table 21 Pn6 Hssio Pinout

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin FPGA Bank PN6_TX_PIN_P0 PN6_TX_PIN_N0 PN6_RX_PIN_P0 PN6_RX_PIN_N0 PN6_TX_PIN_P1 PN6_TX_PIN_N1 PN6_RX_PIN_P1 PN6_RX_PIN_N1 PN6_TX_PIN_P2 PN6_TX_PIN_N2 PN6_RX_PIN_P2 PN6_RX_PIN_N2 PN6_TX_PIN_P3 PN6_TX_PIN_N3 PN6_RX_PIN_P3 PN6_RX_PIN_N3 PN6_TX_PIN_P4 PN6_TX_PIN_N4 PN6_RX_PIN_P4 PN6_RX_PIN_N4 PN6_TX_PIN_P5 PN6_TX_PIN_N5 PN6_RX_PIN_P5 PN6_RX_PIN_N5 PN6_TX_PIN_P6 PN6_TX_PIN_N6 PN6_RX_PIN_P6...

  • Page 35: Pn6 Gpio Pin Map

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 Appendix A.2.1: Pn6 GPIO Pin Map Signal FPGA Pin FPGA Bank FPGA IO Standard GPIO1 LVCMOS15 GPIO2 LVCMOS15 GPIO3 LVCMOS15 GPIO4 LVCMOS15 GPIO5 LVCMOS15 GPIO6 LVCMOS15 GPIO7 LVCMOS15 GPIO8 LVCMOS15 GPIO9 LVCMOS15...

  • Page 36: Table 22 Pn6 Gpio Pin Map

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin FPGA Bank FPGA IO Standard GPIO36 LVCMOS15 GPIO37 LVCMOS15 GPIO38 LVCMOS15 Table 22 : Pn6 GPIO Pin Map Page 30 Rear Connector Pinouts ad-ug-1506_v1_0.pdf...

  • Page 37: Pmc Connector P4

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 Appendix A.3: PMC Connector P4 Signal FPGA Pin P4 Pin P4 Pin FPGA Pin Signal ETH0_MDI0_P* ETH0_MDI2_P * ETH0_MDI0_N* ETH0_MDI2_N * ETH0_MDI1_P* ETH0_MDI3_P * ETH0_MDI1_N* ETH0_MDI3_N * USB1_DM* USB2_DM* USB1_DP* USB2_DP* USB1_VBUS...

  • Page 38: Table 23 Pn4 Interface

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin P4 Pin P4 Pin FPGA Pin Signal F19(PMC MIO37) PS_GPIO2 Table 23 : Pn4 Interface * These FPGA pins are not connect directly to the FPGA, but instead go through an on-board transceiver.

  • Page 39: Appendix B: Front (Xrm) Connector Pinouts

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 Appendix B: Front (XRM) Connector Pinouts The XRM interface consists of two connectors: CN1 and CN2. CN1 is a 180-way Samtec QSH in 3 fields. It is for general purpose signals, power and module control. CN2 is a 28-way Samtec QSE-DP for high-speed serial (MGT) links.

  • Page 40: Xrm Connector Cn1, Field 1

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 Appendix B.1: XRM Connector CN1, Field 1 Signal FPGA Samtec Samtec FPGA Signal DA_N0 DA_N1 DA_P0 DA_P1 DA_N2 DA_P3 DA_P2 DA_N3 DA_N4 AV10 DA_N5 DA_P4 AV11 DA_P5 DA_N6 BB10 DA_N7 DA_P6 BB11...

  • Page 41: Xrm Connector Cn1, Field 2

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 Appendix B.2: XRM Connector CN1, Field 2 Signal FPGA Samtec Samtec FPGA Signal DB_N2 DB_N3 DB_P2 DB_P3 DB_N4 DB_N5 DB_P4 DB_P5 DB_N6 AT13 DB_N7 DB_P6 AT14 DB_P7 DB_N8 DB_P9 DB_P8 DB_N9 DB_P10...
  • Page 42 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Samtec Samtec FPGA Signal MGT_C2M_P7:2 MGT_M2C_P7 MGT_C2M_N7:2 MGT_M2C_N7 Table 25 : XRM Connector CN1, Field 2 Page 36 Front (XRM) Connector Pinouts ad-ug-1506_v1_0.pdf...

  • Page 43: Xrm Connector Cn1, Field 3

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 Appendix B.3: XRM Connector CN1, Field 3 Signal FPGA Samtec Samtec FPGA Signal DC_P2 DC_P3 DC_N2 DC_N3 DC_N4 DC_P5 DC_P4 DC_N5 DC_P6 DC_P7 DC_N6 DC_N7 DC_N8 AJ10 DC_N9 DC_P8 AH11 DC_P9 DC_P10...

  • Page 44: Xrm Connector Cn2

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 Appendix B.4: XRM Connector CN2 Signal FPGA Samtec Samtec FPGA Signal MGT_C2M_P0 MGT_M2C_P0 MGT_C2M_N0 MGT_M2C_N0 MGT_C2M_P1 MGT_M2C_P1 MGT_C2M_N1 MGT_M2C_N1 MGT_C2M_P4 MGT_M2C_P4 MGT_C2M_N4 MGT_M2C_N4 MGT_C2M_P5 MGT_M2C_P5 MGT_C2M_N5 MGT_M2C_N5 MGT_C2M_P2 MGT_M2C_P2 MGT_C2M_N2 MGT_M2C_N2 MGT_C2M_P3...

  • Page 45: Appendix C: Full Pinout Table

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 Appendix C: Full pinout table Signal FPGA Pin LPDDR4_0_CH0_CA_A[0] AK30 LPDDR4_0_CH0_CA_A[1] AJ30 LPDDR4_0_CH0_CA_A[2] AK32 LPDDR4_0_CH0_CA_A[3] AF33 LPDDR4_0_CH0_CA_A[4] AE32 LPDDR4_0_CH0_CA_A[5] AE33 LPDDR4_0_CH0_CA_B[0] AK34 LPDDR4_0_CH0_CA_B[1] AH35 LPDDR4_0_CH0_CA_B[2] AE34 LPDDR4_0_CH0_CA_B[3] AD34 LPDDR4_0_CH0_CA_B[4] AD36 LPDDR4_0_CH0_CA_B[5] AD35...
  • Page 46 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin LPDDR4_0_CH0_DQS_C_B[1] AG41 LPDDR4_0_CH0_DQS_T_B[1] AH42 LPDDR4_0_CH0_DQ_A[0] AM30 LPDDR4_0_CH0_DQ_A[10] AF38 LPDDR4_0_CH0_DQ_A[11] AE39 LPDDR4_0_CH0_DQ_A[12] AD39 LPDDR4_0_CH0_DQ_A[13] AD38 LPDDR4_0_CH0_DQ_A[14] AJ40 LPDDR4_0_CH0_DQ_A[15] AJ38 LPDDR4_0_CH0_DQ_A[1] AL31 LPDDR4_0_CH0_DQ_A[2] AN32 LPDDR4_0_CH0_DQ_A[3] AN33 LPDDR4_0_CH0_DQ_A[4] AM31 LPDDR4_0_CH0_DQ_A[5] AN31 LPDDR4_0_CH0_DQ_A[6]...
  • Page 47 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin LPDDR4_0_CH1_CA_A[1] BB40 LPDDR4_0_CH1_CA_A[2] AV42 LPDDR4_0_CH1_CA_A[3] AU41 LPDDR4_0_CH1_CA_A[4] AT41 LPDDR4_0_CH1_CA_A[5] AT42 LPDDR4_0_CH1_CA_B[0] BA33 LPDDR4_0_CH1_CA_B[1] BA34 LPDDR4_0_CH1_CA_B[2] AV35 LPDDR4_0_CH1_CA_B[3] AV33 LPDDR4_0_CH1_CA_B[4] AU33 LPDDR4_0_CH1_CA_B[5] AU35 LPDDR4_0_CH1_CKE_A[0] AY41 LPDDR4_0_CH1_CKE_A[1] AW40 LPDDR4_0_CH1_CKE_B[0] AY34 LPDDR4_0_CH1_CKE_B[1]...
  • Page 48 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin LPDDR4_0_CH1_DQ_A[10] AT35 LPDDR4_0_CH1_DQ_A[11] AT31 LPDDR4_0_CH1_DQ_A[12] AR32 LPDDR4_0_CH1_DQ_A[13] AT34 LPDDR4_0_CH1_DQ_A[14] AP35 LPDDR4_0_CH1_DQ_A[15] AR31 LPDDR4_0_CH1_DQ_A[1] AV40 LPDDR4_0_CH1_DQ_A[2] BA38 LPDDR4_0_CH1_DQ_A[3] BA39 LPDDR4_0_CH1_DQ_A[4] BB38 LPDDR4_0_CH1_DQ_A[5] BB39 LPDDR4_0_CH1_DQ_A[6] AU40 LPDDR4_0_CH1_DQ_A[7] AU38 LPDDR4_0_CH1_DQ_A[8] AP31 LPDDR4_0_CH1_DQ_A[9]...
  • Page 49 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin LPDDR4_1_CH0_CA_A[4] AJ28 LPDDR4_1_CH0_CA_A[5] AK29 LPDDR4_1_CH0_CA_B[0] AM25 LPDDR4_1_CH0_CA_B[1] AP25 LPDDR4_1_CH0_CA_B[2] AN29 LPDDR4_1_CH0_CA_B[3] AM28 LPDDR4_1_CH0_CA_B[4] AP29 LPDDR4_1_CH0_CA_B[5] AP30 LPDDR4_1_CH0_CKE_A[0] AK26 LPDDR4_1_CH0_CKE_A[1] AL25 LPDDR4_1_CH0_CKE_B[0] AP26 LPDDR4_1_CH0_CKE_B[1] AN25 LPDDR4_1_CH0_CK_C_A[0] AJ27 LPDDR4_1_CH0_CK_T_A[0] AH26 LPDDR4_1_CH0_CK_C_B[0]...
  • Page 50 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin LPDDR4_1_CH0_DQ_A[4] AN23 LPDDR4_1_CH0_DQ_A[5] AJ22 LPDDR4_1_CH0_DQ_A[6] AP23 LPDDR4_1_CH0_DQ_A[7] AH22 LPDDR4_1_CH0_DQ_A[8] AV30 LPDDR4_1_CH0_DQ_A[9] AW30 LPDDR4_1_CH0_DQ_A[10] AV26 LPDDR4_1_CH0_DQ_A[11] AW29 LPDDR4_1_CH0_DQ_A[12] AW27 LPDDR4_1_CH0_DQ_A[13] AV27 LPDDR4_1_CH0_DQ_A[14] AU25 LPDDR4_1_CH0_DQ_A[15] AU29 LPDDR4_1_CH0_DQ_B[0] AY24 LPDDR4_1_CH0_DQ_B[1] BB25 LPDDR4_1_CH0_DQ_B[2]...
  • Page 51 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin LPDDR4_1_CH1_CA_B[1] AP15 LPDDR4_1_CH1_CA_B[2] AN19 LPDDR4_1_CH1_CA_B[3] AM19 LPDDR4_1_CH1_CA_B[4] AL19 LPDDR4_1_CH1_CA_B[5] AM18 LPDDR4_1_CH1_CKE_A[0] BB16 LPDDR4_1_CH1_CKE_A[1] AY17 LPDDR4_1_CH1_CKE_B[0] AN17 LPDDR4_1_CH1_CKE_B[1] AM16 LPDDR4_1_CH1_CK_C_A[0] BA17 LPDDR4_1_CH1_CK_T_A[0] BB18 LPDDR4_1_CH1_CK_C_B[0] AP17 LPDDR4_1_CH1_CK_T_B[0] AP18 LPDDR4_1_CH1_CS_A[0] AY16 LPDDR4_1_CH1_CS_A[1]...
  • Page 52 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin LPDDR4_1_CH1_DQ_A[1] AV15 LPDDR4_1_CH1_DQ_A[2] AU16 LPDDR4_1_CH1_DQ_A[3] AU19 LPDDR4_1_CH1_DQ_A[4] AW15 LPDDR4_1_CH1_DQ_A[5] AW18 LPDDR4_1_CH1_DQ_A[6] AW19 LPDDR4_1_CH1_DQ_A[7] AV18 LPDDR4_1_CH1_DQ_A[8] AL22 LPDDR4_1_CH1_DQ_A[9] AK21 LPDDR4_1_CH1_DQ_B[0] AJ15 LPDDR4_1_CH1_DQ_B[1] AH16 LPDDR4_1_CH1_DQ_B[2] AH17 LPDDR4_1_CH1_DQ_B[3] AJ19 LPDDR4_1_CH1_DQ_B[4] AK15 LPDDR4_1_CH1_DQ_B[5]...
  • Page 53 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin P5_PCIE_TX_P5 P5_PCIE_TX_N5 P5_PCIE_TX_P6 P5_PCIE_TX_N6 P5_PCIE_TX_P7 P5_PCIE_TX_N7 P5_PCIE_RX_P0 AC41 P5_PCIE_RX_N0 AC42 P5_PCIE_RX_P1 AA41 P5_PCIE_RX_N1 AA42 P5_PCIE_RX_P2 P5_PCIE_RX_N2 P5_PCIE_RX_P3 P5_PCIE_RX_N3 P5_PCIE_RX_P4 P5_PCIE_RX_N4 P5_PCIE_RX_P5 P5_PCIE_RX_N5 P5_PCIE_RX_P6 P5_PCIE_RX_N6 P5_PCIE_RX_P7 P5_PCIE_RX_N7 PN6_TX_P0 PN6_TX_N0 PN6_TX_P1...
  • Page 54 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin PN6_TX_P7 PN6_TX_N7 PN6_RX_P0 PN6_RX_N0 PN6_RX_P1 PN6_RX_N1 PN6_RX_P2 PN6_RX_N2 PN6_RX_P3 PN6_RX_N3 PN6_RX_P4 PN6_RX_N4 PN6_RX_P5 PN6_RX_N5 PN6_RX_P6 PN6_RX_N6 PN6_RX_P7 PN6_RX_N7 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11...
  • Page 55 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 AVR_MON_B2U_1V5 AVR_MON_CLK_1V5 AVR_MON_U2B_1V5 CAN_RX_1V8 CAN_TX_1V8 ETH0_MDC ETH0_MDIO ETH0_RXD0 ETH0_RXD1...
  • Page 56 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin ETH0_TXD3 ETH0_TX_CTRL FPGA_USER_SWITCH USER_LED0_1V5_L USER_LED1_1V5_L MBIST_L_1V5 MVMRO_1V5_N PCIE0_MRSTI_1V8_L PCIE0_MRSTI_1V8_L PCIE_MRSTI_L_1V5 PCIE_MRSTO_L_1V5 PCIE_ROOT0_L_1V5 PCIE_WAKE_L_1V5 PMC_SYSMON_SCL PMC_SYSMON_SDA PROGCLK3_P PROGCLK3_N PROGCLK3_P PROGCLK3_N REFCLK100M2_P REFCLK100M2_N REFCLK_300M0_P AF36 REFCLK_300M0_N AF37 REFCLK_300M1_P AR28 REFCLK_300M1_N AT29...
  • Page 57 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin QSPI1_IO1 QSPI1_IO2 QSPI1_IO3 QSPI_CS0_B QSPI_CS1_B ROOT1_L_1V1 AP37 SDIO_CMD_LS SDIO_DAT0_LS SDIO_DAT1_LS SDIO_DAT2_LS SDIO_DAT3_LS SDIO_SEL_LS UART0_485_EN_1V5 UART0_TE485_EN_1V5 UART1_485_EN_1V5 UART0_RX UART0_TX UART1_TX UART1_RX UART1_RX_1V5 UART1_TE485_EN_1V5 UART1_TX_1V5 USB0_CLK USB0_D<0> USB0_D<1> USB0_D<2> USB0_D<3> USB0_D<4>...
  • Page 58 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin XRM_CLKIN_P XRM_DA_CC_N16 AY11 XRM_DA_CC_P16 BA11 XRM_DA_N0 XRM_DA_P0 XRM_DA_N1 XRM_DA_P1 XRM_DA_N2 XRM_DA_P2 XRM_DA_N3 XRM_DA_P3 XRM_DA_N4 AV10 XRM_DA_P4 AV11 XRM_DA_N5 XRM_DA_P5 XRM_DA_N6 XRM_DA_P6 XRM_DA_N7 BB10 XRM_DA_P7 BB11 XRM_DA_N8 XRM_DA_P8 XRM_DA_N9 XRM_DA_P9...
  • Page 59 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin XRM_DB_CC_N16 AT11 XRM_DB_N0 XRM_DB_P0 XRM_DB_N1 AT10 XRM_DB_P1 AR11 XRM_DB_N2 XRM_DB_P2 XRM_DB_N3 XRM_DB_P3 XRM_DB_N4 XRM_DB_P4 XRM_DB_N5 XRM_DB_P5 XRM_DB_N6 XRM_DB_P6 XRM_DB_N7 AT13 XRM_DB_P7 AT14 XRM_DB_N8 XRM_DB_P8 XRM_DB_N9 XRM_DB_P9 XRM_DB_N10 XRM_DB_P10 XRM_DB_N11...
  • Page 60 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin XRM_DC_N0 XRM_DC_P1 XRM_DC_N1 XRM_DC_P2 XRM_DC_N2 XRM_DC_P3 XRM_DC_N3 XRM_DC_P4 XRM_DC_N4 XRM_DC_P5 XRM_DC_N5 XRM_DC_P6 XRM_DC_N6 XRM_DC_P7 XRM_DC_N7 XRM_DC_P8 AH11 XRM_DC_N8 AJ10 XRM_DC_P9 XRM_DC_N9 XRM_DC_P10 XRM_DC_N10 XRM_DC_P11 AG11 XRM_DC_N11 AH10 XRM_DC_P12 XRM_DC_N12...
  • Page 61 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin XRM_DD_N1 XRM_DD_P2 XRM_DD_N2 XRM_DD_P3 XRM_DD_N3 XRM_DD_P4 AF10 XRM_DD_N4 XRM_DD_P5 AE10 XRM_DD_N5 XRM_DD_P6 XRM_DD_N6 XRM_DD_P7 XRM_DD_N7 XRM_DD_P8 XRM_DD_N8 XRM_DD_P9 XRM_DD_N9 XRM_DD_P10 XRM_DD_N10 XRM_DD_P11 XRM_DD_N11 XRM_DD_P12 XRM_DD_N12 XRM_DD_P13 XRM_DD_N13 XRM_DD_P14 XRM_DD_N14...
  • Page 62 ADM-XA210 User Manual V1.0 - Mar 4, 2025 Signal FPGA Pin XRM_SDA_TEST XRM_SD_0 AD11 XRM_SD_1 AD12 XRM_SD_2 AF12 XRM_SD_3 AE11 XRM_MGTCLK_M2C_N XRM_MGTCLK_M2C_P XRM_PECL_N XRM_PECL_P AY10 XRM_PRESENCE_L_1V5 Table 28 : Full Pin Map Page 56 Full pinout table ad-ug-1506_v1_0.pdf...

  • Page 63: Revision History

    ADM-XA210 User Manual V1.0 - Mar 4, 2025 Revision History Date Revision Nature of Change Section 13 Nov 2024 Initial Draft 30 Jan 2025 Initial Release Address: Suite L4A, 160 Dundee Street, Address: 10822 West Toller Drive, Suite 250 Edinburgh, EH11 1DQ, UK...

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