Sony A941 - SPP Cordless Phone Service Schematics page 8

• IC Block Diagrams
U1 U2765B-AFSG3 (BASE RF Board)
U1 U2765B-AFSG3 (HAND RF Board)
28 27 26 25 24 23 22 21 20 19 18 17 16
LOCAL OSC
BUFFER LIMITER DE-
AMP MODULATOR
MIX
LIMITER
RSSI
COMPARATOR
AMP
+
–
A1
1 2 3 4 5 6 7 8 9 10 11 12
U3 TB31202BFN-EL (HAND RF Board)
U10 TB31202BFN-EL (BASE RF Board)
15 14 11
16 13 12
SWITCH
L. OSC
PHASE
1/2
COMPARATOR
OUTPUT
1/2
1
PROGRAMABLE
BUF
––––––––
32, 33
DIVIDER
REFERENCE
DIVIDER
1 PROGRAMABLE
BUF
––––––––
DIVIDER
32, 33
PHASE
1/2
LOCK
COMPARATOR
DET
OUTPUT
2 3
1 4 5 6
U3 CAT93C46KI (BASE MAIN Board)
8 7 6 5
HIGH VOLTAGE
MEMORY ARRAY
GENERATOR
128X8 bit/
64X16 bit
ADDRESS
DECODER
DATA REGISTER
BUFFER
DECODE & CONTROL
LOGIC
CLOCK GENERATOR
1 2 3 4
15
VCC/2
SLICER
+
–
13 14
10 9
BUF
CONTROL
CIRCUIT
7
8
U6 KA8602D (BASE MAIN Board)
RIPPLE
8
BIAS
REJECTION
CIRCUIT
7 MUTE
IN+
1
IN– 2
– + – +
AMP1 AMP2
OUT1 3 6 OUT2
VCC 4 5 GND
– 43 –
U4 TA31103F (BASE MAIN Board)
U7 TA31103F (HAND MAIN Board)
24 23 22 21 20 19
G
–
+
EXP
SUM
MUTE
PRE AMP AMP
VREF
–
VREF
+
THROUGH
VREF THROUG
COMP
MUTE
VREF
FILTER FILTER
IN 2
AMP 2 AMP 1
AMP
+ + +
– – –
G
1 2 3 4 5 6 7
U10 MC74HC595AF (BASE MAIN Board)
16 15 14 13 12 11 10 9
VCC
SHIFT REGISTER
LATCH
GND
1 2 3 4 5 6 7 8
PARALLEL DATA
OUTPUT
18 17 16 15 14 13
–
–
+
+
RO1 SWITCH
AMP RO2 CONTROL
AMP
VREF
SUM VREF
AMP
MIC AMP
+
+
–
–
8 9 10 11 12
U11 LP2953IM (HAND MAIN Board)
GND 1 16 GND
2
NC
OUTPUT 3 15
ERROR
AMP
14
+
–
SENSE
4 13
SHUT DOWN 5
+
–
SHUT DOWN
COMPARATOR
DROP OUT
DETECTION AMP
+
ERROR 6
–
NC
7
GND 8 12
–
1.23V
+
AUXILLARY
COMPARATOR 11
10
9
– 44 –
INPUT
FEEDBACK
5V TAP
VREF
COMP IN
COMP OUT
GND