Pll Circuit - Sharp QA-1650 Service Manual

C164 a0 Glu
RiZ3 C185
10 Gl
vR? BRIGHT
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Fig.12 THRESHOLD LEVEL GENERATOR CIRCUIT
5.PLL CIRCUIT
The dot clock is needed to sample video signals from the computer so as to obtain appropriate dot data.
The dot clock (f,,,) is generated by the PLL circuit in Fig.13. The horizontal sync (f,,) is compared with the feedback
signal (f,) by the PHASE DETECTOR in IC1. When a phase or frequency error occurs between f,,and f.,|C1 PDB
terminal (pin 122) is at a low or high level.
When the phase and frequency of f,, corresponds with those of f., high impedance results. Output signal from the
PDB terminal is converted into DC voltage which controls VCO(Voltage Controlled Oscillator), when passed
through the LOOP FILTER.
VCO is provided with two oscillators (SP1648).IC28 is the oscillator for high band (20.8 to 30.24 MHz), and IC29
the oscillator for low band (14.4 to 20.8 MHz).For these oscillators, oscillation frequency is determined by varac-
tor diode (D2 and 3) capacitance and coil (L3 and 4) inductance.Oscillation frequency is controlled by varying
voltage applied on the varactor diode.
Itis judged by IC2 pin 10 (VCOh) and pin 11 (VCOL) after amplified by transistor (Q6 and 7) which VCO (high or
low band) should be effective. The controlling voltage from the LOOP FILTER varies oscillation frequency ina di-
rection to correct a phase error detected by the PHASE DETECTOR in IC1.
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