NXP Semiconductors i.MX 8MDQLQ User Manual

Hide thumbs

Table of Contents

Quick Links

Download this manual

NXP Semiconductors

User's Guide

i.MX 8MDQLQ Hardware Developer's Guide

1. Overview

This document aims to help hardware engineers design

and test the i.MX 8MDQLQ series processor. It gives

examples on board layout, design checklists to ensure

first-pass success, and solutions to avoid board bring-up

problems.

Engineers should understand board layouts and board

hardware terminology.

This guide is released with relevant device-specific

hardware documentation such as datasheets, reference

manuals, and application notes. All these documents are

available on www.nxp.com/i.MX8M.

Document Number: IMX8MDQLQHDG

Contents

Overview ............................................................................ 1

1.1.

Device supported .................................................... 2

1.2.

Essential references ................................................. 2

1.3.

Supplementary references ....................................... 2

1.4.

Related documentation............................................ 3

1.5.

Conventions ............................................................ 3

1.6.

Acronyms and abbreviations ................................... 4

i.MX 8MDQLQ design checklist ....................................... 5

2.1.

Design checklist table ............................................. 5

2.2.

JTAG signal termination ....................................... 10

i.MX 8MDQLQ layout/routing recommendations ........... 11

3.1.

Introduction........................................................... 11

3.2.

Basic design recommendations ............................. 11

3.3.

Stack-up recommendations ................................... 12

3.4.

DDR design recommendations ............................. 12

3.5.

Trace impedance recommendations ...................... 33

3.6.

Power connectivity/routing ................................... 35

3.7.

USB connectivity .................................................. 37

3.8.

HDMI port connectivity (i.MX 8MDQLQ) .......... 38

3.9.

PCIE connectivity ................................................. 40

3.10.

Unused input/output terminations ......................... 42

Avoiding board bring-up problems .................................. 43

4.1.

Introduction........................................................... 43

4.2.

Avoiding power pitfalls -Current .......................... 43

4.3.

Avoiding power pitfall -Voltage ........................... 43

4.4.

Checking for clock pitfalls .................................... 44

4.5.

Avoiding reset pitfalls ........................................... 45

4.6.

Sample board bring-up checklist ........................... 45

Using BSDL for board-level test ...................................... 47

5.1.

BSDL overview .................................................... 47

5.2.

How BSDL functions ............................................ 47

5.3.

Downloading BSDL files ...................................... 47

5.4.

Pin coverage of BSDL .......................................... 47

5.5.

Boundary scan operation ....................................... 48

5.6.

I/O pin power considerations ................................ 48

Revision history ............................................................... 49

Rev. 2 , 06/2019

Table of Contents

Need help?

Do you have a question about the i.MX 8MDQLQ and is the answer not in the manual?

Questions and answers

Summary of Contents for NXP Semiconductors i.MX 8MDQLQ

Page 1: Table Of Contents
8MDQLQ Hardware Developer’s Guide 1. Overview Contents This document aims to help hardware engineers design Overview ................1 and test the i.MX 8MDQLQ series processor. It gives 1.1. Device supported ............ 2 1.2. Essential references ..........2 examples on board layout, design checklists to ensure 1.3.
Page 2: Device Supported
This Hardware Developer’s Guide supports the i.MX 8MDQLQ (17 x 17 mm package). 1.2. Essential references This guide is supplementary to the i.MX 8MDQLQ series chip reference manuals and data sheets. For reflow profile and thermal limits during soldering, see...
Page 3: Related Documentation
An italicized x indicates an alphanumeric variable. n, m An italicized n indicates a numeric variable. In this guide, notation for all logical, bit-wise, arithmetic, comparison, and assignment operations follow C Language conventions. i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 4: Acronyms And Abbreviations
Power Management Integrated Circuit Power-On Reset Plated Through Hole PCB (i.e. no microvias) RGMII Reduced Gigabit Media Independent Interface (Ethernet) RMII Reduced Media Independent Interface (Ethernet) Read-Only Memory i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 5: I.mx 8Mdqlq Design Checklist
8MDQLQ design checklist 2. i.MX 8MDQLQ design checklist This document provides a design checklist for the i.MX 8MDQLQ (17 × 17 mm package) processor. The design checklist tables recommend optimal design and provide explanations to help users understand better. All supplemental tables referred by the checklist appear in sections following the design checklist tables.
Page 6 GPIO1_IO01, GPIO1_IO02 should be pulled down and GPIO1_IO03, JTAG_nTRST should be pulled — up. Recommended pull resistor value is 4.7 KOhm. Please refer to COMPLIANCE_PATTERNS in the chip BSDL file. i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 7 — — — — VDD_ARM — — — — — VDD_GPU — — — — — VDD_VPU — — — — — VDD_SOC — — — — — i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 8 — — — MIPI_VDDPLL MIPI_VDD and MIPI_VDDA can share the same source. MIPI_VDD — — — — — MIPI_VDD should be isolated with a 120 Ω ferrite bead. i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 9 1. Connect a 499 Ω , 1 % resistor to ground on the — HDMI_REXT ball (ball P1). 2. Route all HDMI differential pairs with 100 Ω — differential impedance. i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 10: Jtag Signal Termination
In normal operation, this pin is internally pulled-up to NVCC_JTAG. But in boundary- scan mode, this pin is floating. An external pull-up resistor is required for boundary- scan mode. i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 11: I.mx 8Mdqlq Layout/Routing Recommendations
8MDQLQ layout/routing recommendations 3. i.MX 8MDQLQ layout/routing recommendations 3.1. Introduction This chapter introduces how to assist design engineers with the layout of an i.MX 8MDQLQ-based system. 3.2. Basic design recommendations When using the Allegro design tool, the schematic symbol & PCB footprint created by NXP is recommended.
Page 12: Stack-Up Recommendations
3.3.1. Stack-up recommendation (i.MX 8MDQLQ) Due to the number of balls on the i.MX 8MDQLQ processor in the 17 mm × 17 mm package, a minimum 8-layer PCB stackup is recommended. Of the 8-layers on the PCB, a sufficient number of layers need to be dedicated to power on routing to meet the IR drop target of 1 % for the i.MX...
Page 13 If it is not possible to place enough ground stitching vias due to space limitation, try to make the length that the signal actually travels on the via as short as possible, as illustrated in Figure i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 14 Z Axis Delay in Setup -> Constraints -> Modes. An example of the delay match calculation has been shown for the i.MX 8MDQLQ EVK board design 18. This analysis was done for the LPDDR4-3200 implementation using the i.MX...
Page 15 Vias are L1-> L8->L1 DRAM_nCS1_A 155.9 Total Net Delay 121.1 36.5 Vias are L1-> L8->L1 DRAM_CKE0_A 157.6 Total Net Delay 106.1 47.4 Vias are L1-> L8->L1 DRAM_CKE1_A 153.5 Total Net Delay i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 16 Figure 2 Figure 5 show the placement and routing of the LPDDR4 signals on the i.MX 8MDQLQ EVK board. The CLK signals are routed on top layer with no via to achieve the best signal quality. Data byte lane 1 signals are routed on layer 4 to make the length that the signal actually travels on the via as short as possible, as limited number of GND vias can be placed near these signal vias.
Page 17 8MDQLQ layout/routing recommendations Figure 2. i.MX 8MDQLQ EVK board LPDDR4 routing (top layer) Figure 3. i.MX 8MDQLQ EVK board LPDDR4 routing (Layer 4) i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 18 8MDQLQ layout/routing recommendations Figure 4. i.MX 8MDQLQ EVK board LPDDR4 routing (Layer 6) Figure 5. i.MX 8MDQLQ EVK board LPDDR4 routing (Layer 8) i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 19 The simulation architecture includes the DDR controller (i.e. the i.MX 8MDQLQ processor), the PCB and the LPDDR4 device. The IBIS model for the i.MX 8MDQLQ processor is available from NXP. The LPDDR4 device IBIS model must be obtained from the memory vendor.
Page 20 7. For DQ nets, bit swapping within each slice/byte lane is OK. 8. For Address nets, use address mirroring to minimize top to bottom stubs. i.MX 8MDQLQ supports address mirroring but the wiring from i.MX 8MDQLQ to the two DRAM ranks must conform to 20, for DDR4 and DDR3L respectively.
Page 21 If it is not possible to place enough ground stitching vias due to space limitation, try to make the length that the signal actually travels on the via as short as possible, as illustrated in Figure i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 22 The delay of the via transitions needs to be included in the overall calculation. This can be realized in Allegro tool by enabling Z Axis Delay in Setup -> Constraints -> Modes. An example of the delay match calculation has been shown for the i.MX 8MDQLQ validation board design in...
Page 23 Vias are L1-> L8->L3->L8 U1.AE20: U4.R8 319.0 Total Net Delay 295.2 40.0 Vias are L1-> L4->L3->L8 U1.AB15: U4.R7 335.2 Total Net Delay 259.7 58.1 Vias are L1-> L4->L6->L8 i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 24 Total Net Delay 273.8 43.1 Vias are L1-> L4->L6->L8 RAS_N U1.AB10: U4.L8 316.9 Total Net Delay 271.7 49.2 Vias are L1-> L8->L3->L8 WE_N U1.AC10: U4.L2 320.9 Total Net Delay i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 25 3.4.3.2. DDR4-2400 Routing Example (i.MX 8MDQLQ) Figure 9 Figure 13 show the placement and routing of the DDR4 signals on the i.MX 8MDQLQ validation board. Figure 9. i.MX 8MDQLQ validation board DDR4 routing (top layer) i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019...
Page 26 8MDQLQ layout/routing recommendations Figure 10. i.MX 8MDQLQ validation board DDR4 routing (Layer 3) Figure 11. i.MX 8MDQLQ validation board DDR4 routing (Layer 4) i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 27 8MDQLQ layout/routing recommendations Figure 12. i.MX 8MDQLQ validation board DDR4 routing (Layer 6) Figure 13. i.MX 8MDQLQ validation board DDR4 routing (Layer 8) i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 28 8MDQLQ layout/routing recommendations 3.4.3.3. DDR3L-1600 routing example (i.MX 8MDQLQ) show the placement and routing of the DDR3L signals on the i.MX 8MDQLQ Figure 14 Figure 18 validation board. Figure 14. i.MX 8MDQLQ validation board DDR3L routing (top layer) Figure 15. i.MX 8MDQLQ validation board DDR3L routing (Layer 3) i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev.
Page 29 8MDQLQ layout/routing recommendations Figure 16. i.MX 8MDQLQ validation board DDR3L routing (Layer 4) Figure 17. i.MX 8MDQLQ validation board DDR3L routing (Layer 6) i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 30 The simulation architecture includes the DDR controller (i.e. the i.MX 8MDQLQ processor), the PCB and the DDR4/DDR3L device. The IBIS model for the i.MX 8MDQLQ processor is available from NXP. The DDR4/DDR3L device IBIS model must be obtained from the memory vendor.
Page 31 3.4.4. i.MX 8MDQLQ DDR package delay When performing the required delay matching for LPDDR4/DDR4 routing, the bond wires within the i.MX 8MDQLQ QM package need to be accounted for and included in the match calculation. Table 24 lists the lengths from each die I/O to the package ball, as well as the propagation/fly time from the die I/O to the package ball.
Page 32 • Match data and CMD trace lengths (allowable delta depends on the access rate being used) • CLK should be longer than the longest signal in the Data/CMD group (+5 mils). i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 33: Trace Impedance Recommendations
85 Ω Differential DDR DQS/CLK, PCIe TX/RX data pairs 90 Ω Differential USB differential signals Differential signals, including Ethernet, PCIe 100 Ω Differential clocks, HDMI, MIPI (CSI and DSI) i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 34 • The skew between HDMI pairs should be within the minimum recommendation (±100 mil). Figure 21. Microstrip and stripline differential pair dimensions Figure 22. Differential pair routing i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 35: Power Connectivity/Routing
There are companion PMICs that provide a low-cost and efficient solution for powering the i.MX 8MDQLQ processor. shows a block diagram of the power tree of the NXP i.MX 8MDQLQ EVK board. It uses a Figure 23 single PF4210 PMIC with several discrete buck converters to power ON rails of the processor.
Page 36 < 22 mΩ Table 28. i.MX 8MDQLQ PDN impedance requirements Ω) Ω) Supply Input < 20 MHz (m 20 - 100 MHz (m VDD_ARM 13.5 VDD_SOC VDD_GPU VDD_VPU VDD_DRAM NVCC_DRAM i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 37: Usb Connectivity
8MDQLQ layout/routing recommendations 3.7. USB connectivity The i.MX 8MDQLQ provides two complete USB3.0 interfaces and the following configurations (or any subset) are supported: • Dedicated host or device using Type-A connector or Type-B connector; • Dual role using Type-C connector.
Page 38: Hdmi Port Connectivity (I.mx 8Mdqlq)
8MDQLQ layout/routing recommendations 3.8. HDMI port connectivity (i.MX 8MDQLQ) The i.MX 8MDQLQ provides an HDMI transmitter capable of supporting an HDMI2.0 compatible output. Figure 24 shows the HDMI connectivity. For the HDMI output, 604 Ω resistors on the positive and negative sides of each high-speed output pair are grounded through a FET.
Page 39 Figure 24. HDMI output connectivity When planning the HDMI interface, place the 604 Ω pull-down resistors directly on the signal trace, as shown in Figure Figure 25. HDMI interface pull-down resistor placement i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 40: Pcie Connectivity
8MDQLQ layout/routing recommendations 3.9. PCIE connectivity The i.MX 8MDQLQ has two PCIE interfaces. Each has a pair of pins with the name of PCIEx_REF_PAD_CLK_P/N. The pins are used to feed 100 MHz reference clock to the PHY from external clock source. They are input-only pins and have no capability to output clock. Do not connect them to PCIE connector or PCIE device.
Page 41 8MDQLQ layout/routing recommendations Figure 27. Reference schematic i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 42: Unused Input/Output Terminations
3.10. Unused input/output terminations 3.10.1. i.MX 8MDQLQ unused input/output guidance For the i.MX 8MDQLQ, the I/Os and power rails of an unused function can be terminated to reduce overall board power. lists connectivity examples for unused power supply rails and...
Page 43: Avoiding Board Bring-Up Problems
• Make two measurements: the first after initial board power-up and the second while running a heavy use-case that stresses the i.MX 8MDQLQ processor. Ensure that the i.MX 8MDQLQ power supply meets the DC electrical specifications as listed in the chip-specific data sheet. See Table 32 for a sample voltage report table.
Page 44: Checking For Clock Pitfalls
Avoiding board bring-up problems NOTE This report table is for the i.MX 8MDQLQ EVK board. Sample voltage reports for customer PCBs will be different from this, depending on the Processor and Power Management IC (PMIC) used and the assignment of the PMIC power resources.
Page 45: Avoiding Reset Pitfalls
• During initial power-on while asserting the POR_B reset signal, ensure that 25 MHz and 27 MHz clock is active before releasing POR_B. • Follow the recommended power-up sequence specified in the i.MX 8MDQLQ data sheet. • Ensure the POR_B signal remains asserted (low) until all voltage rails associated with bootup are The SAI_TXD[0:7], SAI_RXD[0:7], BOOT_MODE[0:1] balls and internal fuses control boot.
Page 46 DDR has been correctly soldered onto the board. Users should recheck the schematic to ensure that the DDR memory has been connected to the i.MX 8MDQLQ correctly. i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 47: Using Bsdl For Board-Level Test
The appearance of linkage in a pin’s file implies that the pin cannot be used with boundary scan. They are usually power pins or analog pins that cannot be defined with a digital logic state. i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 48: Boundary Scan Operation
Therefore, the power supply pin for each specific module must be powered for the IO buffers to operate. This is straightforward for the digital pins within the system. NOTE BSDL was only tested at 1.8 V. i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 49: Revision History
Figure 06/2019 Updated data in Table Table 23, Table Updated to add information related to the Table 6 boundary-scan mode. Added Section 5 Using BSDL for board-level testing. i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide, Rev. 2, 06/2019 NXP Semiconductors...
Page 50 Information in this document is provided solely to enable system and software How to Reach Us: implementers to use NXP products. There are no express or implied copyright licenses Home Page: granted hereunder to design or fabricate any integrated circuits based on the nxp.com information in this document.

NXP Semiconductors i.MX 8MDQLQ User Manual

Quick Links

1. Overview

Need help?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for NXP Semiconductors i.MX 8MDQLQ

Summary of Contents for NXP Semiconductors i.MX 8MDQLQ

Table of Contents