Rohm BD71805MWV Design Manual
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Rohm BD71805MWV Design Manual

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Platform Design Guide
BD71805MWV
(Power Management IC designed for
"Freescale i.MX 6 SoloLite Processors")
Platfrom Design Guide
November 2015
ROHM CONFIDENTIAL
Revision 1.10
ROHM Confidential
Rev.1.10
1/30

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Summary of Contents for Rohm BD71805MWV

  • Page 1 Platform Design Guide BD71805MWV (Power Management IC designed for “Freescale i.MX 6 SoloLite Processors”) Platfrom Design Guide November 2015 ROHM CONFIDENTIAL Revision 1.10 ROHM Confidential Rev.1.10 1/30...

  • Page 2: Revision History

    Updated document name of datasheet. Chapter 4 November ・ Table 4-5-3 1.00 2015 Updated descriptions for termination setting when it is not used. Chapter 2 November 1.10 ・ Fixed descriptions about default OFF rail in each Master/Slave mode. 2015 ROHM Confidential Rev.1.10 2/30...

  • Page 3: Table Of Contents

    4.2.1 Overall component Placement Example ......................... 17 4.2.2 Large Current Loop ..............................18 4.2.3 Power GND ................................. 19 4.2.4 VIN (Power supply for BD71805MWV analog circuit) ..................... 19 4.2.5 Other Signal Pattern Precautions ..........................19 4.2.6 Feedback sense line..............................19 4.3 Switching regulators......................

  • Page 4: Introduction

    3 GPOs. And it is designed to support the specific power requirement of Freescale i.MX 6 SoloLite platforms with minimum cost requirement. The “BD71805MWV Platform Design Guide” provides design guideline which is recommended to PCB layer stack up, the components placement and the PCB routing. To reduce the risk that comes from PCB layout or parts placement, the guideline is strongly recommended to be adapted to the PCB design.

  • Page 5: System Features

    2 System Features BD71805MWV is used to supply the required power to the SoC and peripheral devices. Once powered up, it can be controlled by I2C bus to determine internal settings. The following explains the features that are incorporated in the IC.
  • Page 6 PWRON: Power ON/OFF Control Input  STANDBY: Standby Input for Switching ON / STANDBY Mode  RESETINB: Reset Input to Reset Hung PMIC  POR: Power ON Reset Output  Serial Interface I2C interface provides access to configuration registers.  ROHM Confidential Rev.1.10 6/30...

  • Page 7: General Design Considerations

    3 General Design Considerations This chapter provides general PCB design guidelines such as BD71805MWV general parts placement. 3.1 Package Dimension of BD71805MWV Figure 3-1-1 shows the package dimension of BD71805MWV. BD71805 Lot Number Figure 3-1-1 BD71805MWV Package Dimension ROHM Confidential Rev.1.10...

  • Page 8: Pin Configuration

    3.2 Pin Configuration Figure 3-2-1 shows the BD71805MWV pin configuration with which signals from respective blocks are effectively routed out from PMIC to SoC, SDRAM, and other platform components. PVIN1 RESETINB PVIN1 PGND2 VINL2 PWRON STANDBY MSSEL GPO1 VINL1 GPO2...

  • Page 9: General Stack-Up Recommendations

    3.3 General Stack-up Recommendations Type-3 and 6 layers PCB technology is used for BD71805MWV. The following general stack-up is strongly recommended to be applied to all the routings on the PCB.  Surface plane layer are recommended to be 1.9 Mils thick copper.
  • Page 10 Table 3-5-1: Platform via Examples Via type Hole size Pad size Anti-Pad size Plated through-hole (PTH) 12 mils 24 mils 32 mils Hole size Pad size Anti-Pad size Figure 3-5-1: Dimension of via ROHM Confidential Rev.1.10 10/30...

  • Page 11: Bd71805Mwv Breakout Example

    For the breakout routing on Layer 1(Top layer) thru 6 (Bottom layer), refer to Figure 3-6-1 thru Figure 3-6-6. BUCK3 BUCK4 VODVREF LDO1-3 BUCK1 Crystal SNVSCAP /VOSNVS BUCK2 Figure 3-6-1 BD71805MWV Reference Board Breakout and Parts Placement (Top Layer) ROHM Confidential Rev.1.10 11/30...
  • Page 12 Figure 3-6-2 BD71805MWV Reference Board Breakout (Layer 2) VSYS Figure 3-6-3 BD71805MWV Reference Board Breakout (Layer 3) ROHM Confidential Rev.1.10 12/30...
  • Page 13 Figure 3-6-4 BD71805MWV Reference Board Breakout (Layer 4) Figure 3-6-5 BD71805MWV Reference Board Breakout (Layer 5) ROHM Confidential Rev.1.10 13/30...
  • Page 14 Figure 3-6-6 BD71805MWV Reference Board Breakout (Layer 6) ROHM Confidential Rev.1.10 14/30...

  • Page 15: Platform Power Delivery Guidelines

    It is essential to follow the guidelines for stable power delivery to the SoC and the system. 4.1 Platform Power Delivery Figure 4-1-1-1 and Figure 4-1-1-2 show the voltages BD71805MWV provides to the SoC and the other devices in the system and Table 4-1-1-1 and Table 4-1-1-2 provide the maximum current guideline for respective voltage rail.
  • Page 16 LIB Charger 1.2V BUCK2 NVCC_DRAM PWRON Core1 1.8V 1.2V Core2 POWER KEY (LPDDR2) 0.6V DVREF (½*DVREFIN) PMIC Figure 4-1-1-1: BD71805MWV Power Delivery Map (Slave mode) 3.15V eMMC 3.15V 3.15V Touch H:VSYS 3.15V WiFi PMIC MSSEL 3-GPO Mode Select Xtal 3.15V...

  • Page 17: General Layout Guideline

    Figure 4-2-1 shows the overall component-placement example. The figure shows the components that are needed to put closely to the BD71805MWV. It is strongly recommended that power components are put prior to any other components so that the signals do not interfere with each other.

  • Page 18: Large Current Loop

    VIN (input voltage) and power ground (GND). PVIN1 PGND1 COUT Figure 4-2-2-2: Example of parts placement and routing in the top layer of a buck regulator (BUCK1) ROHM Confidential Rev.1.10 18/30...

  • Page 19: Power Gnd

    Thus, power grounds should take large area as much as possible to keep impedance low and reduce the swing ground voltage level. 4.2.4 VIN (Power supply for BD71805MWV analog circuit) VIN should not connect with plane VSYS directly to avoid external noise from PVINx due to common impedance.

  • Page 20: Switching Regulators

    As output capacitors, use one 10uF capacitors. LX1[1:0] <The recommended spec of capacitor is shown below.> 1. Size: 0402, capacitance: 10uF± 20%, tolerance: 6.3V Connect to BUCK1 output voltage which is regulated by the DC/DC converter of BD71805MWV. ROHM Confidential Rev.1.10 20/30...

  • Page 21: Buck2

    BUCK2 is a high-efficiency single buck regulator with integrated FET that converts the VSYS voltage to a regulated voltage. This VR can dynamically change its output voltage setting using the I2C interface. BUCK2 output voltage range is from 0.8V to 2.0V (25mV/ step). 4.3.2.1 Schematic Example Figure 4-3-2-1 BUCK2 Schematic Example ROHM Confidential Rev.1.10 21/30...
  • Page 22 <The recommended spec of capacitor is shown below.> 1. Size: 0402, capacitance: 10uF± 20%, tolerance: 6.3V Connect to BUCK1 output voltage which is regulated by the DC/DC converter of BD71805MWV. 4.3.2.4 Layout Example Figure 4-3-2-2 BUCK2 Layout Example (Top Layer) ROHM Confidential Rev.1.10...

  • Page 23: Buck3

    As output capacitors, use one 10uF capacitors. LX3[1:0] <The recommended spec of capacitor is shown below.> 1. Size: 0402, capacitance: 10uF± 20%, tolerance: 6.3V Connect to BUCK1 output voltage which is regulated by the DC/DC converter of BD71805MWV. ROHM Confidential Rev.1.10 23/30...

  • Page 24: Buck4

    Figure 4-3-3-2 BUCK3 Layout Example (Top Layer) 4.3.4 BUCK4 BUCK4 is a high-efficiency single buck regulator with integrated FET that converts the VSYS voltage to a regulated voltage. 4.3.4.1 Schematic Example Figure 4-3-4-1 BUCK4 Schematic Example ROHM Confidential Rev.1.10 24/30...
  • Page 25 <The recommended spec of capacitor is shown below.> 1. Size: 0402, capacitance: 10uF± 20%, tolerance: 6.3V Connect to BUCK1 output voltage which is regulated by the DC/DC converter of BD71805MWV. 4.3.4.4 Layout Example Figure 4-3-4-2 BUCK4 Layout Example (Top Layer) ROHM Confidential Rev.1.10...

  • Page 26: Linear Vr

    <The recommended spec of capacitor is shown below.> 1. Size: 0402, capacitance: 1.0uF± 10%, tolerance: 6.3V As output capacitors, use one 1.0uF capacitor. <The recommended spec of capacitor is shown below.> 1. Size: 0402, capacitance: 1.0uF± 10%, tolerance: 6.3V ROHM Confidential Rev.1.10 26/30...

  • Page 27: Vodvref

    If VODVREF is used by register control, VODVREF can be used. In this case, as output capacitors, use one 1.0uF capacitor. <The recommended spec of capacitor is shown below.> 1. Size: 0402, capacitance: 1.0uF± 10%, tolerance: 6.3V ROHM Confidential Rev.1.10 27/30...

  • Page 28: Snvscap / Vosnvs

    <The recommended spec of capacitor is shown below.> 1. Size: 0402, capacitance: 1.0uF± 10%, tolerance: 6.3V SNVSCAP [MSSEL=L (Master mode)] As output capacitors, use one 1.0uF capacitor. <The recommended spec of capacitor is shown below.> 1. Size: 0402, capacitance: 1.0uF± 10%, tolerance: 6.3V ROHM Confidential Rev.1.10 28/30...

  • Page 29: Interfaces

    Connect to a thermistor via 5.1kΩ resistor 5.1K Ohm pull-up to Connect to Battery Thermistor CHGREF (NTC=10K Ohm) Connect to a current sense resistor individually BATTP for accurate sensing Connect to a current sense resistor individually BATTN for accurate sensing ROHM Confidential Rev.1.10 29/30...

  • Page 30: Rtc

    Connect to SoC (default) Connect to SoC 4.5.6 MISC Table4-5-6 Schematic checklist of MISC System Termination Signal Pin Names Dir. Pull-up/Pull-down if it is not Notes Check Voltage Level (RTT) used MISC GND[1:0] Connect to GND plane GNDT1 ROHM Confidential Rev.1.10 30/30...

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