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Advanced Chipset Features
DRAM Timing Selectable
CAS Latency Time
DRAM RAS# to CAS# Delay
DRAM RAS# Precharge
Precharge Delay <tRAS>
System Memory Frequency
SLP_S4# Assertion Width
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole At 15M-16M
** VGA Setting **
PCI/Onchip VGA Control
On-Chip Frame Buffer Size
DVMT Mode
DVMT/FIXED Memory Size
Boot Display
Panel Number
↑↓→←
: Move
F5: Previous Values
The screen above list all the fields available in the Advanced Chipset Features
submenu, for ease of reference in this manual. In the actual CMOS setup, you have
to use the scroll bar to view the fields. The settings on the screen are for refer-
ence only. Your version may not be identical to this one.
This section gives you functions to configure the system based on
the specific features of the chipset. The chipset manages bus speeds
and access to system memory resources.
be altered unless necessary.
because they provide the best operating conditions for your system.
The only time you might consider making any changes would be if
you discovered some incompatibility or that data was being lost
while using your system.
DRAM Timing Selectable
This field is used to select the timing of the DRAM.
By SPD
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
By SPD
Auto
Auto
Auto
Auto
Auto
4 to 5 Sec.
Enabled
Disabled
Disabled
Onchip VGA
8MB
DVMT
128MB
CRT
3:1024*768(18 bit)
Enter: Select
+/-/PU/PD: Value
F6: Fail-Safe Defaults
The default settings have been chosen
The EEPROM on a DIMM has SPD (Serial Pres-
ence Detect) data structure that stores informa-
tion about the module such as the memory type,
memory size, memory speed, etc. When this op-
tion is selected, the system will run according to
the information in the EEPROM. This option is the
default setting because it provides the most sta-
BIOS Setup
Item Help
Menu Level
F10: Save
ESC: Exit
F1: General Help
F7: Optimized Defaults
These items should not
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