Analog Devices ADN8810 Application Note page 4

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AN-619

DEMO BOARD SCHEMATIC AND LAYOUT

Figure 7 shows the schematic for the ADN8810 demo

board. JP1 is the address header where jumpers can

short 1–2, 3–4, and 5–6.

The board is constructed with four layers. PVDD and

AVDD are split on one middle layer, and VSS and GND

are split on another. All four layers and the top overlay

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Figure 7. ADN8810 Demo Board v2.0 Schematic

labels are shown in Figure 8. The board perimeter is

included in all figures for reference.

The top and bottom layers show copper traces. However,

the VSS/GND and PVDD/AVDD layers are split planes and

their figures show where copper is removed. Note that

both sets of split planes are electrically isolated from each

other. For single-supply operation, both VSS and GND

must be connected to 0 V.

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