DTK PAM-0075I User Manual page 41

High performance pentium pci atx mainboard
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DRAM Read Burst (EDO/FP): This sets the timing for burst mode reads from DRAM:
x444/x444
x333/x444
x222/x333
DRAM Write Burst Timing: This sets the timings for burst write to DRAM:
x444
x333
x222
Fast EDO Lead Off: Select Enabled only for EDO DRAMs in either a synchronous cache or a
cacheless system. It causes a 1-HCCK pull-in all read leadoff latencies for EDO DRAMs. Select
Disabled if any of the DRAM rows are populated with FPM DRAMs.
SDRAM (CAS Lat/RAS-to-CAS): It is used to set the CAS# latency and the RAS to CAS delay
for all SDRAM cycles.
SDRAM (CAS Lat/RAS-to-CAS)
3/3
2/2
3/2
SDRAM Speculative Read: If Enabled, the CPU will issue predict commands to access the
DRAM. If a miss occurs, the CPU will cancel this command. Some operating systems under
certain situations have a problem utilizing this feature so it is normally Disabled.
System BIOS Cacheable: Selecting Enabled allows caching of the system BIOS ROM at
F0000h-FFFFFh, resulting in better system performance. However, if any program writes to this
memory area, a system error may result.
Video BIOS Cacheable: Selecting Enabled allows caching of the video BIOS ROM at C0000h to
C7FFFh, resulting in better video performance. However, if any program writes to this memory
area, a system error may result.
Read EDO and FP DRAM Timings are x-4-4-4.
Read EDO DRAM Timings are x-3-3-3, and FP DRAM
s are x-4-4-4.
Read EDO DRAM Timings are x-2-2-2, and FP DRAM
s are x-3-3-3.
Write DRAM timings are x-4-4-4
Write DRAM timings are x-3-3-3
Write DRAM timings are x-2-2-2
CAS# latency
3 Clock
2 Clock
3 Clock
Award BIOS Setup Guide
RAS to CAS delay
3 Clock
2 Clock
2 Clock
35

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