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Teledyne SP Devices ADQ3 Series User Manual

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ADQ3 Series FWDAQ
Author(s):
Teledyne SP Devices
Document ID:
20-2507
Classification:
Public
Revision:
B
Print date:
2022-03-31
Development Kit
User Guide

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Summary of Contents for Teledyne SP Devices ADQ3 Series

  • Page 1 ADQ3 Series FWDAQ Development Kit User Guide Author(s): Teledyne SP Devices Document ID: 20-2507 Classification: Public Revision: Print date: 2022-03-31...

  • Page 2: Table Of Contents

    5.8 Record ..........ADQ3 Series FWDAQ Development Kit spdevices.com...
  • Page 3 9.1.2 Connecting to the Debug Core ......ADQ3 Series FWDAQ Development Kit spdevices.com...
  • Page 4 Print date 20-2507 2022-03-31 Document History Revision Date Section Description Author 2022-03-31 Updated for ADQ36-PXIe release TSPD 2021-11-16 Add section on user logic 2 port control TSPD 2021-06-21 Initial revision TSPD ADQ3 Series FWDAQ Development Kit spdevices.com Page 3 of 38...

  • Page 5: Introduction

    2022-03-31 1 Introduction This document is the user guide for the development kit of the data acquisition firmware for ADQ3 series digitizers. There are different versions of the development kit depending on the device-to-host interface and the target number of channels. Make sure the development kit matches the target hardware.

  • Page 6: Prerequisites

    2 Prerequisites The development kit has the following prerequisites: • A license for the development kit purchased from Teledyne SP Devices. • A license for the Xilinx design tools. For current versions of the development kit, a license for Vivado 2020.2 is required.

  • Page 7: Development Environment And Tools

    The Tcl file that is sourced to enable the development kit. Note  Apart from the file config.vh (see Section 3.3.1, the files in the framework directory are not intended to be edited by the end user. ADQ3 Series FWDAQ Development Kit spdevices.com Page 6 of 38...

  • Page 8: Opening The Development Kit

    Tcl console. The project is now ready to be set up for first-time use. Note  The development kit for ADQ3 series digitizers works differently compared to previous products since building the user logic areas no longer requires special Tcl commands. See Section for details.

  • Page 9: Building The Design

    Generate the FPGA configuration file (.mcs file) by using one of the two methods outlined below: • Automatic Execute the command devkit_build in the Tcl console. • Manual ADQ3 Series FWDAQ Development Kit spdevices.com Page 8 of 38...

  • Page 10: Analyzing The Implemented Design

    The report is divided into six different sections. Each section has several parameters and result values. For parameters with a maximum value the format is Percentage[Value/Maximum value] (Difference) ADQ3 Series FWDAQ Development Kit spdevices.com Page 9 of 38...
  • Page 11 The report contains the following sections: Critical warnings These warnings must be fixed, or at least, well understood. CDC Critical Check the reports/post_impl.rpt for details. Synth Critical Check the reports/synth_runme.log for details. ADQ3 Series FWDAQ Development Kit spdevices.com Page 10 of 38...
  • Page 12 UltraFast Design Methodology [2]. Excessive usage may lead to difficulty in reaching the timing goals. Route CPU time Route CPU time is the process time used during route. ADQ3 Series FWDAQ Development Kit spdevices.com Page 11 of 38...
  • Page 13 However, due to Vivado’s optimization efforts, there may be reports if significant timing issues are introduced in the user logic. If the user logic is well timed and excessive logic levels are still reported, please contact TSPD support. ADQ3 Series FWDAQ Development Kit spdevices.com Page 12 of 38...

  • Page 14: General Concepts

    This section introduces concepts surrounding the development kit based on FWDAQ for ADQ3 series digitizers. Please refer to the ADQ3 Series FWDAQ User Guide [3] for the base knowledge on how the digitizer operates. The reader is assumed to be familiar with digital design in general and this section only serves to highlight some important aspects of digital design with respect to the development kit.
  • Page 15 Classification Revision Public Document ID Print date 20-2507 2022-03-31 Figure 3: A block diagram of the data path of FWDAQ. The two user logic areas are highlighted in green. ADQ3 Series FWDAQ Development Kit spdevices.com Page 14 of 38...

  • Page 16: Clock Domain Crossing Synchronization

    A clock domain crossing, CDC, is a boundary where digital signals pass from one clock domain to another. This boundary constitutes a critical point in the design and care must be taken to synchronize signals ADQ3 Series FWDAQ Development Kit spdevices.com...

  • Page 17: Cdc Synchronization Of A 1-Bit Signal

    ENABLE_OUTPUT_REGISTER since the registers used for the CDC synchronization will prevent the auto- matic replication performed by Vivado to reduce fanout. By adding the additional register, this situation is avoided. ADQ3 Series FWDAQ Development Kit spdevices.com Page 16 of 38...

  • Page 18: Cdc Synchronization Of A Multi-Bit Signal

    In most cases there is no need to clear the output registers in cdc_bus and it advised to tie src_rst_i low. It shall not be connected to a global reset as this will have negative impact on timing. ADQ3 Series FWDAQ Development Kit spdevices.com...

  • Page 19: Axi Control Bus

    ReadUserRegister() • WriteUserRegister() • Refer to the ADQ3 series user guide [3] for the API documentation. Note  Transactions on the control bus cannot be initiated from the user design, only from calling specific functions in the ADQAPI.
  • Page 20 Figure 4: A diagram showing the principle of extracting signals from and inserting signals into the data bus. Any field not inserted manually is subjected to a pipeline delay equal to the value of the BUS_PIPELINE parameter. ADQ3 Series FWDAQ Development Kit spdevices.com Page 19 of 38...

  • Page 21: Data Bus Signals

    1) to channel B and so on. Important  Bus signals not mentioned in this section are not yet implemented. Do not interact with these signals from the development kit. ADQ3 Series FWDAQ Development Kit spdevices.com Page 20 of 38...

  • Page 22: Timestamp

    The counter value during a data clock cycle where record start is asserted propagates to the user’s application via the record header— provided the mechanism is set up and activated. ADQ3 Series FWDAQ Development Kit spdevices.com Page 21 of 38...

  • Page 23: Event

    The inhibit signal is controlled by the trigger blocking mechanism. The signal is one bit wide and a logic high level implies that triggers are blocked, i.e. trigger events are not converted into records by the acquisition module. Conversely, a logic low level implies that triggers are accepted. ADQ3 Series FWDAQ Development Kit spdevices.com Page 22 of 38...

  • Page 24: Overrange

    The signals may not be asserted in the same data clock cycle. ADQ3 Series FWDAQ Development Kit spdevices.com Page 23 of 38...
  • Page 25 Note that it is valid to create an infinite stream of data by generating a single record start event. Listed below is a summary of the properties of the record bits. ADQ3 Series FWDAQ Development Kit spdevices.com Page 24 of 38...
  • Page 26 5.10 Differences relative to ADQ14, ADQ7 and ADQ8 This section provides a short list of notable differences in the ADQ3 series digitizers data buses compared to previous digitizers is provided to help with migrating a design.
  • Page 27 The register access is controlled in the module instantiating the register file, i.e. (in user_logic1.v). To construct a register with read and write access, connect the two corresponding ports of the register ADQ3 Series FWDAQ Development Kit spdevices.com Page 26 of 38...
  • Page 28 This range always reads as 0x00abcdef with the default user logic contents. However, the value can be changed by modifying the HDL design. Name UL1CONTROL Offset Default This register contains the control bit for the simple test pattern generator described in Section 6.1. ADQ3 Series FWDAQ Development Kit spdevices.com Page 27 of 38...
  • Page 29 The resulting range will be interpreted as a 2’s complement value. ADQ3 Series FWDAQ Development Kit spdevices.com Page 28 of 38...
  • Page 30 Example  With a base value of 1000 and a parallelization of 8, the generator will output 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, 1000, 1001, 1002, ... ADQ3 Series FWDAQ Development Kit spdevices.com Page 29 of 38...
  • Page 31 This section documents the register file for an unmodified version of the development kit. Name UL2ID Offset 0x12345678 Default This register contains a constant value to identify the first user logic area. ID[31:24] ID[23:16] ID[15:8] ID[7:0] ADQ3 Series FWDAQ Development Kit spdevices.com Page 30 of 38...
  • Page 32 The default value is 0, leaving the data for each channel unmodified. Name UL2BASEVALUE Offset Default This register contains the base value used by the simple test pattern generator described in Section 7.1. BASEVALUE[31:24] BASEVALUE[23:16] BASEVALUE[15:8] BASEVALUE[7:0] ADQ3 Series FWDAQ Development Kit spdevices.com Page 31 of 38...
  • Page 33 The resulting range will be interpreted as a 2’s complement value. ADQ3 Series FWDAQ Development Kit spdevices.com Page 32 of 38...
  • Page 34 The input value for a pin is always accessible from the user logic area, while control of the output value and the direction requires changing the pin’s function to ADQ_FUNCTION_USER_LOGIC. This is a configu- ration parameter set from software, please refer to the ADQ3 Series FWDAQ User Guide [3] for more information on how to change port functions.
  • Page 35 PXIE, containing two pins using differential signaling. The pins have fixed direction. ext_starb_i — input value of the PXIe STARB pin. – ext_starc_o — output value of the PXIe STARC pin. – ADQ3 Series FWDAQ Development Kit spdevices.com Page 34 of 38...
  • Page 36 Review the failing paths and surrounding logic in Vivado’s schematic viewer. Carefully review that you conform with the recommendations in Timing ClosureQuick Reference Guide (UG1292)” [5]. For detailed information see UltraFast Design Methodology User Guide Guide (UG949) [2]. ADQ3 Series FWDAQ Development Kit spdevices.com Page 35 of 38...
  • Page 37 EnableErrorTrace() with the trace_level argument set to 3. If the error message is difficult to interpret, the Teledyne SP Devices support can be reached via e-mail at spd_support@teledyne.com. Make sure to include a trace log file from a run where the error appears.
  • Page 38 • Program the firmware image (.mcs file) using ADQUpdater. Refer to the ADQUpdater user guide for instructions on how to manage the firmware on the ADQ3 series digitizer [1]. 9.1.2 Connecting to the Debug Core The Vivado hardware manager is used to connect to the debug core. Connecting to the debug core requires: that the .mcs file with core has been programmed;...
  • Page 39 [2] Xilinx Inc., UltraFast Design Methodology, August 2020. User Guide Guide (UG949). [3] Teledyne Signal Processing Devices Sweden AB, 21-2539 ADQ3 Series FWDAQ User Guide. Tech- nical Manual. [4] C. E. Cummings, “Clock domain crossing (CDC) design & verification techniques using SystemVer- ilog,”...
  • Page 40 Phone: +46 (0)13 645 0600 Fax: +46 (0)13 991 3044 Email: spd_info@teledyne.com Copyright © 2022 Teledyne Signal Processing Devices Sweden AB All rights reserved, including those to reproduce this publication or parts thereof in any form without permission in writing from Teledyne SP Devices.

This manual is also suitable for:

Adq32-pcieAdq33-pcieAdq36-pxie

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