Table of Contents
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1
Pin No.
Pin Name
61
DSPPW
A
ysslock
62
63
DACRX
64
AKDRDY
65
AKRDY
66
32KSW
67
AKCKS1
aksrst
68
akirst
69
akrq
70
yssr1
71
yssic
72
ysscs
73
B
74
CKSO
75
AVSS
76
NC
77
VREF
78
AVCC
79
YSSRX
80
YSSTX
* PD5967A
C
1
20
D
E
F
40
1
2
I/O
Format
Function and Operation
O
C
DSP : Power supply output
I
C
YSS : PLL lock detection terminal
I
C
DAC : Communication data input
AK7730 : DRDY detection terminal
I
C
I
C
AK7730 : RDY detection terminal
AKMCK switch (fs32K) H : 32kHz L : Others
O
C
O
C
AK7730 : Master clock selection pin 1
O
C
AK7730 : System reset pin
O
C
AK7730 : Initial reset pin
O
C
AK7730 : Request pin
O
C
YSS : PLL initialization signal output terminal
O
C
YSS : Reset terminal
O
C
YSS : Chip select
C
AK7730 : Clock switch
C
Analog GND
Not used
C
A/D : Reference voltage
C
Analog power supply
I
C
YSS : Communication data input
O
C
YSS : Communication data output
Format
C
N
60
PQ1X331M2ZP
41
V
IN
GND
V
c
PQ1X251M2ZP
DEQ-P8000/UC
2
3
Meaning
CMOS
N channel open drain
1
Controller
2
3
1
Vin
GND
2
Controller
Vc
3
3
4
5
V
o
4
N
R
5
Vo
4
Nr
4
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