Enhanced Parallel Port Mode; Extended Capabilities Port Mode; Parallel Interface Programming - HP Deskpro EX Technical Reference Manual

5.5.2 ENHANCED PARALLEL PORT MODE

In Enhanced Parallel Port (EPP) mode, increased data transfers are possible (up to 2 MB/s) due to
a hardware protocol that provides automatic address and strobe generation. EPP revisions 1.7 and
1.9 are both supported. For the parallel interface to be initialized for EPP mode, a negotiation
phase is entered to detect whether or not the connected peripheral is compatible with EPP mode. If
compatible, then EPP mode can be used. In EPP mode, system timing is closely coupled to EPP
timing. A watchdog timer is used to prevent system lockup.
Five additional registers are available in EPP mode to handle 16- and 32-bit CPU accesses with the
parallel interface. Address decoding includes address lines A0, A1, and A2.

5.5.3 EXTENDED CAPABILITIES PORT MODE

The Extended Capabilities Port (ECP) mode, like EPP, also uses a hardware protocol-based design
that supports transfers up to 2 MB/s. Automatic generation of addresses and strobes as well as Run
Length Encoding (RLE) decompression is supported by ECP mode. The ECP mode includes a bi-
directional FIFO buffer that can be accessed by the CPU using DMA or programmed I/O. For the
parallel interface to be initialized for ECP mode, a negotiation phase is entered to detect whether
or not the connected peripheral is compatible with ECP mode. If compatible, then ECP mode can
be used.
Ten control registers are available in ECP mode to handle transfer operations. In accessing the
control registers, the base address is determined by address lines A2-A9, with lines A0, A1, and
A10 defining the offset address of the control register. Registers used for FIFO operations are
accessed at their base address + 400h (i.e., if configured for LPT1, then 378h + 400h = 778h).
The ECP mode includes several sub-modes as determined by the Extended Control register. Two
submodes of ECP allow the parallel port to be controlled by software. In these modes, the FIFO is
cleared and not used, and DMA and RLE are inhibited.

5.5.4 PARALLEL INTERFACE PROGRAMMING

Programming the parallel interface consists of configuration, which typically occurs during POST,
and control, which occurs during runtime.
Compaq Deskpro EX Series of Personal Computers
First Edition - August 2000
Technical Reference Guide
5-11