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Functional Description
3.7
Clock Distribution
The PCIE-6002 utilizes the PCI Express common clock architecture with the upstream host
providing the reference clock. A low-jitter fanout buffer is used to provide this clock to the
PEX and each M.2 or NGFF socket. A 32.768kHz PCI Express suspend clock is generated
on-board and provided to each M.2 or NGFF socket.
3.8
Reset Control
In addition to responding to the PCI Express fundamental reset, each installed M.2 AHCI
or NVMe SSD module can be individually controlled via the NVMe Reset Status or Control
register.
40
PCIE-6002 Installation and Use (6806800U70B)
Functional Description
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