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BVM BVME310 User Manual

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Manual P/N 454-48019
This material contains information of proprietary interest to BVM Ltd. It has been supplied in
confidence and the recipient, by accepting this material, agrees that the subject matter will not be
copied or reproduced, in whole or in part, nor its contents revealed in any manner or to any person
except to meet the purposes for which it was delivered.
User's Manual
BVME310
MC68000
16-BIT PROCESSOR BOARD
Board Revision E / E1
Manual Revision H February 17, 1997
BVM Limited,
Hobb Lane,
Hedge End,
Southampton,
SO30 0GH, UK.
TEL: +44 (0)1489 780144
FAX: +44 (0)1489 783589
E-MAIL: sales@bvmltd.co.uk
WEB: http://www.bvmltd.co.uk

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  • Page 1 Board Revision E / E1 Manual Revision H February 17, 1997 This material contains information of proprietary interest to BVM Ltd. It has been supplied in confidence and the recipient, by accepting this material, agrees that the subject matter will not be copied or reproduced, in whole or in part, nor its contents revealed in any manner or to any person except to meet the purposes for which it was delivered.
  • Page 2 BVM Ltd. This applies to any merged, modified or derivative version USE OF PRODUCT...

  • Page 3: Table Of Contents

    3.10 Local Bus Monitor ........................6 3.11 LED Indicators..........................6 4. VMEbus Installation ..........................7 5. Configuration ............................8 5.1 BVME310 PCB Layout ........................8 5.2 Link Definitions..........................8 5.2.1 FL1 EPROM Size Select ................... 8 5.2.2 JPRB Interrupt Handler Options................9 5.2.3 FL2 VMEbus ACFAIL Interrupt Enable..............10 5.2.4 JPRC System Controller Functions.
  • Page 4 8.1 On-Board Functions ........................19 8.2 VMEbus Master..........................19 8.3 VMEbus System Controller Functions ..................19 8.4 Board Configuration ........................20 8.5 Operating Environment ........................20 Appendix A - Data Sheets & Manual References..................21 Appendix B - Circuit Diagrams ......................22 Copyright © 1997 BVM Ltd.

  • Page 5: Introduction

    1.2 Part Numbers 451-48011 3U VME 68000 CPU Module operating at 10MHz, with 512Kbytes EPROM and 512Kbytes SRAM. 451-48013 3U VME 68000 CPU Module operating at 10MHz, with 512Kbytes EPROM, 2Mbytes SRAM, 128bytes E PROM and RTC. Copyright © 1997 BVM Ltd.

  • Page 6: Overview

    VMEbus Interrupt handler 7 level, Vectored and Autovectored. • System Controller Functions:- Single level Arbiter. RESET, SYSCLK generator Bus timeout BERR generator. • Single slot 3U form factor. • Fully compatible to VMEbus specification revision C.1. • Full OS9 Software support. Copyright © 1997 BVM Ltd.

  • Page 7: Applications

    BVME310 2.2 Applications • VMEbus Main System processor. • Multi Processing Node. • Industrial Control. Copyright © 1997 BVM Ltd.

  • Page 8: Operation

    BVME310 3. Operation 3.1 Block Diagram 3.2 Processor The BVME310 is based on the MC68HC000 16-bit Quad processor a low power version of the 68000. The module has been designed to operate at 10MHz. 3.3 Memory EPROM The BVME310 can support 128K, 256K or 512Kbytes of zero wait state ROM in the two JEDEC sockets.

  • Page 9: Interrupts

    3.6 Interrupts 3.6.1 VMEbus Interrupt Handler The BVME310 will support VMEbus interrupts on any of 7 levels. A jumper link is provided to allow each Interrupt level to individually enabled. A VMEbus interrupt causes the CPU to reply with a VMEbus Master Interrupt acknowledge cycle. This cycle uses only IACK that is broadcast in a similar way to the addresses.

  • Page 10: Vmebus System Controller Functions

    SRAM storage can be used to allow access to a configuration program. 3.10 Local Bus Monitor The BVME310 provides a 25.6 µ S a local Bus Timeout BERR signal for internal accesses, BERR for external accesses is set by the system controller.

  • Page 11: Vmebus Installation

    BVME310 4. VMEbus Installation The BVME310 module is inserted into a vacant VMEbus slot. If it is to function as the system controller, then it should be positioned in the left most slot. It passes through all VMEbus daisy chained arbitration signals.

  • Page 12: Configuration

    5.2 Link Definitions The following link definitions show the links grouped in the same orientation as the layout drawing above, i.e. the VMEbus P1 connectors to the left. Link positions marked with a › show the BVME310 default configuration. The following features on the BVME310 are all link selectable:- 5.2.1 FL1 EPROM Size Select...

  • Page 13: Jprb Interrupt Handler Options

    VME IRQ1 Vectored JPRB is used to select the interrupt sources for the BVME310 as shown in the table above. It is recommended that for a level where more than one interrupt source is available, only one is chosen except ABORT and VMEbus ACFAIL where both may be set to generate IRQ7. FL2 may also be used to select VMEbus ACFAIL, and when set will be enabled regardless of the setting on JPRB.

  • Page 14: Fl2 Vmebus Acfail Interrupt Enable

    7 & 8 Fitted › VMEbus SGL Arbiter Enabled. (Level 3) JPRC is used to enable the system controller functions, when the BVME310 is the System controller all links should be fitted. Link position 1 & 2 enables a push button Reset or a Power up Reset to generate a VMEbus Reset when fitted.

  • Page 15: Jpre Parallel Sense Block

    VME BERR if any cycle on the VMEbus lasts longer than 25.6 µ S. Link position 7 & 8 enables the BVME310 to operate as the single level SGL arbiter when fitted. SGL arbitration operates on level 3 only.

  • Page 16: Fl3 68681 Ip5 Source

    EEPROM to be read, however on this variant the status can be set by the user. 5.3 Indicators RED LED Indicates the BVME310 is the current VMEbus Master. GREEN LED Indicates processor currently running valid code. The LED will be extinguished by a RESET.

  • Page 17: Connector Pinouts

    +5V STDBY +12V Signals shown in the shaded boxes are not used. The following signals are not required by the BVME310, but have been connected onboard to preserve the VMEbus daisy chain:- IACKIN is connected to IACKOUT, BG0IN is connected to BG0OUT, BG1IN is connected BG1OUT BG2IN is connected to BG2OUT.

  • Page 18: Ja & Jb Serial Port Connections

    (IDC) and ribbon cable. Not all the RS232 signals defined for a 25 way connector are supported by the BVME310. The cable assembly should be built such that pin 1 on the 14 way connector connects to pin 1 of the 25 way.

  • Page 19: Programming

    VMEbus location that does not return a DTACK within this period. The CPU bus error timeout period for the BVME310 is 25.6 µ S. The CPU bus error timer is also dependant on VMEbus error which the BVME310 monitors.

  • Page 20: Eprom

    16 Bit Access: Read/Write The BVME310 is factory fitted with 512Kbytes of SRAM on the 451-48011 or 2Mbytes on the 451- 48013. The memory which is accessed as a 16-bit block again provides zero wait state access to the CPU.

  • Page 21: Non Volatile Eeprom (451-48013 Only)

    For further information refer to the MC68681 Data sheet, see Appendix Appendix A . 7.6 Non Volatile EEPROM (451-48013 only) The 451-48013 variant of the BVME310 provides a serial access 1024-bit electrically erasable PROM (EEPROM) that is typically used to hold configuration data. The EEPROM is organized as 64x16-bit registers.

  • Page 22: Vmebus Master Access

    Appendix Appendix A . 7.7 VMEbus Master Access The BVME310 can access VMEbus as a bus master. Depending on the Address Range used, different types of access are performed. VMEbus specifies three basic Address Mode schemes - A16 (Short I/O), A24 (Standard) and A32 (Extended).

  • Page 23: Specification

    25.6 µ S LOCAL BUS TIMEOUT GREEN LED Indicates CPU Running Valid Code. RED LED Indicates BVME310 is current VMEbus Master. RESET Switch. ABORT Switch (Generates an Autovectored 7 Interrupt if enabled). 8.2 VMEbus Master Single Level 3 Requester A24, A16 D16, D08(EO) Interrupt handler D08(O): I(1-7) all levels, link selectable.

  • Page 24: Board Configuration

    EPROM Size Select; VMEbus SYSCLOCK enable; 8.5 Operating Environment Dimensions: 100mm x 160mm (3U) single slot. Power: +5V 0.9A Typ +12V 30mA, -12V 30mA Environmental: 0 to 70 ° C, 95% humidity non-condensing (extended range to order). Copyright © 1997 BVM Ltd.

  • Page 25: Appendix A - Data Sheets & Manual References

    Configurable with Extended Voltage (2.7V to 5.5V) (MICROWIRE ™ Bus Interface) Data Sheet (1996 Sheet No. TL/D/11330) DS1215 DALLAS Semiconductors DS1215 Phantom Time Chip Data Sheet (1993 Sheet No. 021894) VMEbus The VMEbus SPECIFICATION (Sept 1987, VITA) Copyright © 1997 BVM Ltd.

  • Page 26: Appendix B - Circuit Diagrams

    BVME310 Appendix B - Circuit Diagrams Copyright © 1997 BVM Ltd.
  • Page 27 /ACFAIL /IRQ7 /ACFAIL /IRQ7 310CNTRLISP JPRB /IRQ7 /ABORT /ABORT Title RPIN30 RPIN30 /ABORT /VIRQ7 /VIRQ7 /IRQ6 /VIRQ6 BVME310 MC68000 CPU Module /VIRQ6 /IRQ5 /VIRQ5 BVM Ltd. /VIRQ5 Issue Dwg No. Size /IRQ4 /VIRQ4 /VIRQ4 Hobb Lane. /IRQ3 /SERIRQ BVM00784 /SERIRQ...
  • Page 28 YOUT /BR3 /VBR1 /VBR2 /BR3 74F243 74F786 330R 330R LED1 LED2 GREENLED REDLED /GREENLED /REDLED Title BVME310 MC68000 CPU Module BVM Ltd. 100nF 10uF Issue Dwg No. Size Hobb Lane. BVM00784 Hedge End Date Southampton SMRNET8 SMRNET8 Sheet 2 of 3...
  • Page 29 100nF 100nF 220pF SW PUSHBUTTON 10uF 10uF 10uF +12V -12V +12V -12V 100nF 100nF Title BVME310 MC68000 CPU Module BVM Ltd. Issue Dwg No. Size Hobb Lane. BVM00784 Hedge End Date Southampton Sheet 3 of 3 10th August 1998 SO30 0GH...

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