Nibble Mode; Ecp Mode - Canon QY8-1360-000 Service Manual

BJC-7100

2.1.2 Nibble mode

In nibble mode, 8-bit data is sent from the printer to the host PC in two 4-bit blocks.
The printer lowers the DataAvail signal when it is ready to send data to the host PC.
After confirming the fall in the HostBusy signal, the printer prepares 8 bits of data
and outputs the low 4 bits on the control signal line on the fall in the PtrClk signal.
When the PtrClk signal drops, the host PC fetches the data and raises the HostBusy
and PtrClk signals.
Next, when the printer has confirmed the second drop in the HostBusy signal, it
outputs the high 4 bits of data to the control signal line. If, after the HostBusy signal
has risen, there is no more data to be sent to the host PC, the DataAvail signal rises
and the printer enters a standby state until there is more data to be sent.
1284Active
(Selectin)
AckDataReq
(PE)
HostBusy
(Autofd)
HostClk
(Strobe)
PtrClk
(Ack)
PtrBusy
(Busy)
DataAvail
(Fault)
Xflag
(Select)

2.1.3 ECP mode

Because data is sent and received in both directions on the data bus in ECP mode,
data can be received at high speed. Because control signals can be used to separate
data from commands, and bidirectional communication can be established within this
mode, there is no need to switch to other modes when switching the direction in
which data is being sent.
The data bus switches direction from forward to reverse data transmission in
response to a fall in the AckReverse (PE) signal from the printer.
The data bus switches direction from reverse to forward data transmission in
response to a rise in the ReverseRequest (Init) signal.
High
Status maintained.
Data Available
Nibble Mode Support
Figure 4-7 Interface Timing (Nibble Mode)
1284Active
(Selectin)
AckReverse
(PE)
Data 1-8 Input
HostAck
(Autofd)
HostClk
(Strobe)
0MIN
PeriphClk
(Ack)
PeriphAck
(Busy)
PeriphRequest
(Fault)
XFlag
(Select)
35msMax
ReverseRequest
(Init)
Foward Phase Foward to
Reverse
Figure 4-8 Interface Timing (ECP Mode)
Bit2 Bit6
35msMax
35msMax
35msMax
500msMax
Bit3 Bit7
Bit0 Bit4
Bit1 Bit5
Output Valid Valid
35msMax
Data=High
Command=Low
Reverse Phase
4-7
Part 4: Technical Reference
Input
35msMax
Foward
Phase