Acer AS8950G Service Manual page 161

Table 4-2. SEC Phase POST Code Table:
Functionality Name (Include\
PostCode.h)
SEC_FORCE_MAX_RATIO*
SEC_GO_TO_SECSTARTUP
SEC_GO_TO_PEICORE
* 3rd party relate functions – Platform dependence.
Table 4-3. PEI Phase POST Code Table:
Functionality Name (Include\
PostCode.h)
PEI_SIO_INIT P
PEI_CPU_REG_INIT P
PEI_CPU_AP_INIT* P
PEI_CPU_HT_RESET*
PEI_PCIE_MMIO_INIT P
PEI_NB_REG_INIT P
PEI_SB_REG_INIT
PEI_PCIE_TRAINING*
PEI_TPM_INIT P
PEI_SMBUS_INIT P
PEI_PROGRAM_CLOCK_GE
N
PEI_IGD_EARLY_INITIAL *
PEI_HECI_INIT*
PEI_WATCHDOG_INIT*
PEI_MEMORY_INIT P
PEI_MEMORY_INIT_FOR_CR
ISIS
PEI_MEMORY_INSTALL PEI
PEI_TXTPEI*
PEI_SWITCH_STACK
PEI_MEMORY_CALLBACK P
PEI_ENTER_RECOVERY_MO
DE
Troubleshooting
Phase PostCode
SEC 08
SEC 09
SEC 0A
Phase Post Code
EI 70
EI 71
EI 72
PEI 73
EI 74
EI 75
PEI 76
PEI 77
EI 78
EI 79
PEI 7A
PEI 7B
PEI 7C
PEI 7D
EI 7E
PEI 7F
80
PEI 81
PEI 82
EI 83
PEI 84
Description
Tune CPU frequency ratio to
maximum level
Setup BIOS ROM cache
Enter Boot Firmware Volume
Description
Super I/O Initialization
CPU Early Initialization
Multi-processor Early Initial
HyperTransport Initialization
PCIE MMIO BAR Initialization
North Bridge Early Initialization
South Bridge Early Initialization
PCIE Training
TPM Initialization
SMBUS Early Initialization
Clock Generator Initialization
Internal Graphic device early
Initialization
HECI Initialization
Watchdog timer Initialization
Memory Initial for Normal boot.
Memory Initial for Crisis Recovery
Simple Memory test
TXT function early Initialization
Start to use Memory
Set cache for physical memory
Recovery device Initialization
4-17