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Pin No.
Pin Name
7
AVDD
8
VIN1
9
AGND
10~12
VIN2~4
13
AVDD
14~16
VIN5~7
17
AGND
18
LPFOUT2
19
AVDD
20
REFP2
21
CM2
22
REFN2
23
AGND
24
ADVDD
25
ADGND
26
DVDDCO
27
DGNDCO
28
SLEEP
29
RESET_L
30~33
MODE [3] ~ [0]
34
DVDDIO
35
DGNDIO
36~38
INS [2] ~ [0]
39~42
GAINS [3] ~ [0]
43
INSSEL
44
PLLSEL
45
DVDDCO
46
CLKX2
47
DGNDCO
48
HSYNC_L
49
VSYNC_L
50
DVDDIO
51
DGNDIO
52~59
C [0] ~ [7]
60
DGNDCO
61
CLKX2O
62
CLKXO
63
DGNDCO
64~71
Y [0] ~ [7]
72
SAS
73
SCL
KRF-V7300D/V8300D/V9300D
CIRCUIT DESCRIPTION
I/O
-
Analog power supply.
I
Analog video signal input port-1.
-
Analog GND.
I
Analog video signal input port-2.
-
Analog power supply.
I
Analog video signal input port-5 to 7.
-
Analog GND.
O
Analog amp output-2.
-
Analog power supply.
O
ADC2 reference voltage.
O
ADC2 reference voltage.
O
ADC2 reference voltage.
-
Analog GND.
-
Digital power supply for analog circuit.
-
Digital GND for analog circuit.
-
Digital core power supply.
-
Digital core GND.
I
Sleep signal input port.
I
Reset signal input port.
I
Mode setting port-3 to 0.
-
Digital I/O power supply.
-
Digital I/O GND.
I
Input signal selector port-2 to 0.
I
Analog amp gain setting port-3 to 0.
I
Setting port for input signal selector.
I
Setting port for PLL clock.
-
Digital core power supply.
I
External clock signal input port.
-
Digital core GND.
O
Horizontal synchronizing signal output port.
O
Vertical synchronizing signal output port.
-
Digital I/O power supply.
-
Digital I/O GND.
O
Color-difference signal output port-0 to 7.
-
Digital core GND.
O
System clock output port.
O
Pixel clock output port.
-
Digital core GND.
O
Luminance signal output port-0 to 7.
I
Setting for slave address.
I
IIC bus clock input port.
Description
Logic
3.3V
composite
composite or luminance
3.3V
color-difference signal
open
3.3V
open
open
open
3.3V
2.5V
3.3V
2.5V
3.3V
[0]; LSB, [7]; MSB
[0]; LSB, [7]; MSB
21
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