Yamaha YSP-1000 Service Manual page 68

A B C
YSP-1000
SCHEMATIC DIAGRAM (OPERATION)
1
2
OPERATION (4)
Page 63 L6
3 to DSP_CB7
Page 67 E8
to INPUT (3)_W401
4
5
-22.5
6
-17.8
-16.2
-22.5
-24.1
-24.1
-17.7
-17.8
-19.3
-19.3
-19.3
3.3 3.3 3.3
-17.8
-22.4 -22.4
-22.4
7
-22.5 -22.5 -22.5
8
9
10
# All voltages are measured with a 10MΩ/V DC electronic volt meter.
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
68
D E F
5.1 6.8
12.0
5.1
8
5.1
5
5.1
7 5.1
6 1.4
5.1
6.8
0 0 2
1
1.4 4.8
0 4
3
0 0
FL DISPLAY
3.3 3.3 3.3
-17.8
-17.9 -22.5
-17.8
-24.7 -17.8 -22.5
-22.5
-16.2
-19.3
-17.8
-17.8
-17.9
-17.8
3.3
-24.7
3.3 3.3
1.5
1.5
-19.3
0
FL DRIVER
-19.2 -24.1
3.2
3.2
3.2
3.2
G H I
OPTIMAIZER MIC
5.1
0
OPERATION (3)
-24.1
-17.5
12.0
4.6
4.9
4.9
4.6
4.6
0
0 0.3
IR-IN
0 3.3
0
OPERATION (1)
J K L
Page 63 L5
to DSP_CB6
FRONT SW
OPERATION (2)
IC801: NJM2068MD-TE2 IC1: M66003-0101FP
Dual OP-Amp FL Display Driver
OUT 1 8 +V
1 CC
–IN 1 2 7 OUT 2
+ – + –
+IN 1 3 6 –IN 2
/CEFL 2 Serial
receive
–V 4 5 +IN CKFL 3
CC 2
circuit
DTFL 4
XIN 7
Clock
generator
XOUT 6
/RESET 1
VDD 8
Vcc2 18
Vss 5
Vp 64
M N
Display code
CGROM
RAM
44 P35
(8-bit x 60) (35 bit x 166)
Segment 19 P10
Code
output
write 17 P9
circuit
CGROM
9 P1
dot data
data (35 bit x 16)
write
Code/
command
45 P36
control
circuit
52 G12
G13
51
code Segment
50 G14
select
digit
select/
49
output
timing Display
clock controller scan pulse circuit
48
47 P38
46 P37
63 G1
Digit
output
circuit
53 G11