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USB_SSTX0+
B23
USB_SSTX0-
B22
USB_SSRX0+
A23
USB_SSRX0-
A22
USB_SSTX1+
B26
USB_SSTX1-
B25
USB_SSRX1+
A26
USB_SSRX1-
A25
USB_HOST_PRSNT
B96
LVDS Signals Descriptions
Signal
Pin#
LVDS_A0+
A71
LVDS_A0-
A72
LVDS_A1+
A73
LVDS_A1-
A74
LVDS_A2+
A75
LVDS_A2-
A76
LVDS_A3+
A78
LVDS_A3-
A79
LVDS_A_CK+
A81
LVDS_A_CK-
A82
LVDS_VDD_EN
A77
LVDS_BKLT_EN
B79
LVDS_BKLT_CTRL
B83
LVDS_I2C_CK
A83
LVDS_I2C_DAT
A84
LPC Signals Descriptions
Signal
Pin#
LPC_AD0
B4
LPC_AD1
B5
LPC_AD2
B6
LPC_AD3
B7
LPC_FRAME#
B3
LPC_DRQ0#
B8
LPC_DRQ1#
B9
LPC_SERIRQ
A50
LPC_CLK
B10
SPI Signals Descriptions
Signal
Pin#
SPI_CS#
B97
SPI_MISO
A92
SPI_MOSI
A95
SPI_CLK
A94
SPI_POWER
A91
BIOS_DIS0#
A34
BIOS_DIS1#
B88
Chapter 3 Hardware Installation
Chapter 3
AC Coupling capacitor
O PCIE
AC coupled on Module
AC Coupling capacitor
I PCIE
AC coupled off Modul
AC Coupling capacitor
O PCIE
AC coupled on Module
AC Coupling capacitor
I PCIE
AC coupled off Modul
I CMOS
3.3V Suspend/3.3V
NA
Pin Type
Pwr Rail /Tolerance
AL9A2
O LVDS
LVDS
O LVDS
LVDS
O LVDS
LVDS
O LVDS
LVDS
O LVDS
LVDS
O CMOS
3.3V / 3.3V
O CMOS
3.3V / 3.3V
O CMOS
3.3V / 3.3V
I/O OD CMOS 3.3V / 3.3V
PU 4.7K to 3.3V
I/O OD CMOS 3.3V / 3.3V
PU 4.7K to 3.3V
Pin Type
Pwr Rail /Tolerance
AL9A2
I/O CMOS
3.3V / 3.3V
O CMOS
3.3V / 3.3V
I CMOS
3.3V / 3.3V
I/O CMOS
3.3V / 3.3V
O CMOS
3.3V / 3.3V
Pin Type
Pwr Rail /Tolerance
AL9A2
O CMOS
3.3V Suspend/3.3V
Connect a series resistor 33
I CMOS
3.3V Suspend/3.3V
Connect a series resistor 33
O CMOS
3.3V Suspend/3.3V
Connect a series resistor 33
O CMOS
3.3V Suspend/3.3V
Connect a series resistor 33
O
3.3V Suspend/3.3V
I CMOS
NA
PU 10K to 3.3V
Connect 90
@100MHz Common Choke in series
Additional transmit signal differential pairs for the SuperSpeed USB data path.
and ESD suppressors to GND to USB connector
Connect 90
@100MHz Common Choke in series
Additional receive signal differential pairs for the SuperSpeed USB data path.
and ESD suppressors to GND to USB connector
Connect 90
@100MHz Common Choke in series
Additional transmit signal differential pairs for the SuperSpeed USB data path.
and ESD suppressors to GND to USB connector
Connect 90
@100MHz Common Choke in series
Additional receive signal differential pairs for the SuperSpeed USB data path.
and ESD suppressors to GND to USB connector
Module USB client may detect the presence of a USB host. A high value (NA for AL9A2)
NA
indicates that a host is present.
Carrier Board
Description
Connect to LVDS connector
Connect to LVDS connector
LVDS Channel A differential pairs
Connect to LVDS connector
Connect to LVDS connector
Connect to LVDS connector
LVDS Channel A differential clock
Connect to enable control of LVDS panel power
LVDS panel power enable
circuit
Connect to enable control of LVDS panel backlight
LVDS panel backlight enable
power circuit.
Connect to brightness control of LVDS panel
LVDS panel backlight brightness control
backlight power circuit.
Connect to DDC clock of LVDS panel
I2C clock output for LVDS display use
Connect to DDC data of LVDS panel
I2C data line for LVDS display use
Carrier Board
Description
LPC multiplexed address, command and data bus
Connect to LPC device
LPC frame indicates the start of an LPC cycle
LPC serial DMA request
LPC serial interrupt
LPC clock output - 33MHz nominal
Carrier Board
Description
Connect a series resistor 33
to Carrier
Chip select for Carrier Board SPI - may be sourced from chipset SPI0 or SPI1
Board SPI Device CS# pin
Connect a series resistor 33
to Carrier
Data in to Module from Carrier SPI
Board SPI Device SO pin
Connect a series resistor 33
to Carrier
Data out from Module to Carrier SPI
Board SPI Device SI pin
Connect a series resistor 33
to Carrier
Clock from Module to Carrier SPI
Board SPI Device SCK pin
Power supply for Carrier Board SPI – sourced from Module – nominally
3.3V. The Module shall provide a minimum of 100mA on SPI_POWER.
Carriers shall use less than 100mA of SPI_POWER. SPI_POWER
shall only be used to power SPI devices on the Carrier
Selection straps to determine the BIOS boot device.
The Carrier should only float these or pull them low, please refer to
COM Express Module Base Specification Revision 2.1 for strapping options of BIOS disable signals.
18
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