Advanced Chipset Features - Acer Veriton 2800 Service Manual

Advanced Chipset Features

DRAM Timing Selectable
x CAS Latency Time
x DRAM RAS# to CAS# Delay
x DRAM RAS# Precharge
x Precharge delay (tRAS)
SLP_S4# Assertion Width
** VGA Setting **
On-chip Video Memory Size
PEG/Onchip VGA Control
DVMT Mode
Parameter
CAS Latency TIme
DRAM RAS# to CAS# Delay This field lets you insert a timing delay between the CAS
DRAM RAS# Precharge
TIme
Precharge Delay
On Chip Memory Size
PEG/Onchip VGA Control
DVMT Mode
26
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
By SPD
Auto
Auto
Auto
Auto
4 to 5 Sec.
[Press Enter]
[Auto]
[DVMT]
:Move Enter: Select +/-/ :Value ESC:Exit F1:General Help
F6:Load Optimized Defaults F7:Load Fail-Safe Defaults
When synchronous DRAM is installed, the number of clock
cycles of CAS latency depends on the DRAM timing.
and RAS strobe signals, used when DRAM is written to,
read from, or refreshed, Fast gives faster performance; and
Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system.
If an insufficient number of cycles is allowed for the RAS to
accumulate its charge before DRAM refresh, the refresh
may be incomplete and the DRAM may fail to retain data.
Fast fives faster performance; and Slow gives more stable
performance.This field applies only when synchronous
DRAM is installed in the syste.
This option is used to set up the timing delay between the
SDRAM active to precharge.
Select the on chip memory size for VGA drive use.
This option is used to control the VGA
This option is used to select the video mode.
Description
Help Item
Menu Level
Options
5,4,3,6,Auto
2,3,4,5,6,Auto
2,3,4,5,6,Auto
4,5,6,7,8,9,10,11,
12,Auto
Onchip VGA
PEG Port
Auto
Fixed,DVMT,Both
Chapter 2