Core Post Codes - Acer Aspire 7730 Series Service Manual

POST Code
0xF3 #define MEM_ERR_RCVEN_FINDCENTER
(CalibrateRcvenForGroup)
0xFZ #define MEM_ERR_TYPE (S11, S04)
0xF5 #define MEM_ERR_RAWCARD (S11)
0xFA #define MEM_ERR_SFF (ProgWrioDll)
0xFB #define MEM_ERR_THERMAL (ProgramThrottling)
0xA0xx Launch BIOS ACMSclean
0xA4xx Launch BIOS ACMScheck
0xE5 Wait for ME ready
0xE6 ME Ready

Core POST Codes

The following table details the core POST codes and functions used in the POST.
POST Code
0x00 Early Microcode update for CAR
0x01 Enable CAR
0x02 CAR Done, initial stack
0xEE unknown CPU ID to load uCode
0xEF unknown DT CPU to load uCode
0xnn File count found in a volume
0x11 Debug Test driver for debug test PPI 1 (If install
debugTest driver)
0x22 Debug Test driver for debug test PPI 2 (If install
debugTest driver)
0x33 Debug Test driver for debug test PPI 3 (If install
debugTest driver)
0x44 Entry point of loadfile
0x88 Entry point of apMuLoader
0x80 A PEIM found
0x82 PEIM not dispatched yet
0x84 PEIM satisfies depex
0x86 Image loaded but fail on security
0x88 Executing a PEIM
0x8A Processing notify event for newly installed PPI
0x8C Handing off to next phase (DXE)
0x8F Fail to hand off to next phase, system halt
0x90 All PEIM dispatched! Going to DxeIpl
0xCC AP Micro-code update
0x20 S3 resume entry
0x21 Start running Boot-time bootscripts
0x22 Start running Run-time bootscripts
0x23 End of S3 resume, jump back to Waking vector
0x80 Initialize the chipset
0x81 Initialize the bridge
Chapter 4
Function
Function
Phase Component
PEI chipset/MRC
PEI chipset/MRC
PEI chipset/MRC
PEI chipset/MRC
PEI chipset/MRC
PEI chipset/TXT
PEI chipset/TXT
DXE HECI/iAMT
DXE HECI/iAMT
Phase Component
CEI / SEC Core
CEI / SEC Core
CEI / SEC Core
CEI / SEC CPU
CEI / SEC CPU
PEI Core
PEI Core
PEI Core
PEI Core
PEI Core
PEI Core
PEI Core
PEI Core
PEI Core
PEI Core
PEI Core
PEI Core
PEI Core
PEI Core
PEI Core
PEI Core
S3 resume Core
S3 resume Core
S3 resume Core
S3 resume Core
Crisis Recovery Core
Crisis Recovery Core
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