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39VF0207CWHP02 (IC511) : EEPROM
1. Pin layout
A11
1
A9
2
A8
3
A13
4
A14
5
A17
6
WE#
7
VDD
8
NC
9
A16
10
A15
11
A12
12
A7
13
A6
14
A5
15
A4
16
2. Block diagram
Memory Address
Address Buffer & Latches
CE#
OE#
WE#
3. Pin function
Symbol
Pin name
AMS- A0
Address Inputs
DQ7- DQ0
Data Input/Output
CE#
Chip Enable
OE#
Output Enable
WE#
Write Enable
VDD
Power Supply
Vss
Ground
NC
No Connection
32
OE#
31
A10
30
CE#
29
DQ7
28
DQ6
27
DQ5
26
DQ4
25
DQ3
24
Vss
23
DQ2
22
DQ1
21
DQ0
20
A0
19
A1
18
A2
17
A3
X-Decoder
Control Logic
Function
To provide memory address. During Sector-Erase AMS-A12 address
lines will select the sector.
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs
are in tri-state when OE# or CE# is high.
To active the device when CE# is low.
To gate the data output buffers.
To control the write operations.
To provide power supply voltage: 3.0-3.6V for SST39LF512/010/020/040
Unconnected Pins
EEPROM
Cell Array
Y-Decoder
I/O Buffers & Data Latches
DQ7~DQ0
2.7-3.6V for SST39VF512/010/010/040
RX-8022PSL
1-21
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