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Summary of Contents for MYiR FZ3
- Page 1 FZ3 Deep Learning Accelerator Card Hardware Manual FZ3 Deep Learning Accelerator Card Hardware Manual Version V1.0 MYiR-Tech | www.myirtech.com 1 / 27...
- Page 2 FZ3 Deep Learning Accelerator Card Hardware Manual Revision History Version Description Date V1.0 Initial Version 2020/06/23 MYiR-Tech | www.myirtech.com 2 / 27...
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Page 3: Table Of Contents
FZ3 Deep Learning Accelerator Card Hardware Manual Table of contents Table of contents ....................... 3 Chapter 1 Overview ......................5 1.1 Product Description ....................... 5 1.2 Picture..........................5 Chapter 2 SOC introduction ..................... 6 2.1 SoC features........................6 2.2 SoC BANK ......................... 8 Chapter 3 Onboard Resources .................. - Page 4 FZ3 Deep Learning Accelerator Card Hardware Manual 4.3 PL Unit ........................... 19 4.3.1 MIPI-CSI ....................... 19 4.3.2 BT1120 ......................... 19 4.3.3 Expansion IO ....................... 20 4.4 Other interface ......................21 4.4.1 Power input ......................21 4.4.2 RTC bat connector....................21 4.4.3 Fan connector......................
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Page 5: Chapter 1 Overview
Chapter 1 Overview 1.1 Product Description The FZ3 Deep learning computing card is an embedded intelligent AI development platform with Xilinx XCZU3EG as the core launched by Shenzhen Myir Technology Co., Ltd. Using Xilinx's latest 16nm process-based Xilinx Zynq UltraScale + MPSoC platform, integrated quad-core Cortex ™... -
Page 6: Chapter 2 Soc Introduction
FZ3 Deep Learning Accelerator Card Hardware Manual Chapter 2 SOC introduction 2.1 SoC features The XCZU3EG used in this development platform belongs to the Zynq UltraScale + MPSoC series SoC, integrating ARM quad-core Cortex-A53 (PS), dual-core Cortex-R5 (PS), Mali-400 MP2 graphics processing unit and Kintex Ultrascale + FPGA (PL). The... - Page 7 FZ3 Deep Learning Accelerator Card Hardware Manual Processing System (PS) Processor Core: Quad-core ARM Cortex-A53 MPCore up to 1.5GHz Maximum Frequency: 1.5Ghz APU: L1 Cache 32KB I / D per core, L2 Cache 1MB. RPU：L1 Cache 32KB I / D per core.
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Page 8: Soc Bank
FZ3 Deep Learning Accelerator Card Hardware Manual 2.2 SoC BANK Figure 2-2 XCZU3EG SFVC784 Banks BANK 0 : humidity Sensor, XADC , Other configuration signals BANK 24：PL HD BANK, 24Pin(12 pairs of differential signal) BANK 25：PL HD BANK, 24Pin(12 pairs of differential signal) ... -
Page 9: Chapter 3 Onboard Resources
FZ3 Deep Learning Accelerator Card Hardware Manual Chapter 3 Onboard Resources 3.1 Hardware resources Figure 3-1 Hardware resources 2GB/4GB DDR4 SDRAM（64bit 2400Mbps） 8GB eMMC 32MB QSPI Gigabit Ethernet RS485*1，CAN*1 Peripheral interface and resources ... -
Page 10: Boot Mode & Jtag Mode
FZ3 Deep Learning Accelerator Card Hardware Manual 1 Channel MIPI-CSI interface，1 Channel BT1120 interface 1 Channel JTAG interface，1 Channel USB to UART debug interface 2 Channel 40PIN 2.54mm spacing IO expander 4 onboard LED status indicators 3.2 Boot Mode &... - Page 11 FZ3 Deep Learning Accelerator Card Hardware Manual Figure 3-4-1 The development Board incorporates 1 Quad-SPI Flash(MT25QU256ABA1EW9-0SI T)，Connect to the QSPI0 interface of the CPU—PS_MIO0 ~ PSMIO5 pins of BANK500: PS_MIO0 QSPI_LOWER_SCK PS_MIO1 QSPI_LOWER_D1 PS_MIO2 QSPI_LOWER_D2 PS_MIO3 QSPI_LOWER_D3 PS_MIO4 QSPI_LOWER_D0 PS_MIO5...
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Page 12: Emmc
FZ3 Deep Learning Accelerator Card Hardware Manual 3.4.2 eMMC Figure 3-4-2 Onboard Micron 8GB eMMC -- MTFC8GAKAJCN-4M IT，8 bit interface，Connectted to CPU SDIO1-- PS_MIO13 ~ PS_MIO23 pins of BANK500: PS_MIO13 SD0_EMMC_D0 PS_MIO14 SD0_EMMC_D1 PS_MIO15 SD0_EMMC_D2 PS_MIO16 SD0_EMMC_D3 PS_MIO17 SD0_EMMC_D4 PS_MIO18... -
Page 13: Erthernet
FZ3 Deep Learning Accelerator Card Hardware Manual 3.5 Erthernet Figure 3-5 The PS unit of Zynq UltraScale + contains a Gigabit Ethernet MAC hardware controller, and an Ethernet physical layer transmission chip needs to be connected to the outside. The development board uses AR8035-AL1B-R as the PHY, and uses the PS RGMII interface to connect a Gigabit Ethernet mouth. -
Page 14: Usb
FZ3 Deep Learning Accelerator Card Hardware Manual 3.6 USB Figure 3-6 Zynq ’s PS-side USB controller is connected to a SMSC company ’s USB PHY chip USB3320C to form a USB 2.0 port as a USB Host, and then expands four USB2.0 ports through GL852G. -
Page 15: Multi-Channel Programmable Clock Generator
FZ3 Deep Learning Accelerator Card Hardware Manual 3.7 Multi-channel programmable clock generator This development platform has a programmable IDT SI5332 I2C programmable clock generator. This clock IC generates the necessary clock for the entire system through external 26 MHz crystal oscillator after frequency multiplication and frequency division processing. - Page 16 FZ3 Deep Learning Accelerator Card Hardware Manual set to high impedance, the watchdog does not work. You can set PS_MIO41 to high impedance during the debugging phase Watchdog work is prohibited. The TPS3828-33DBVT also has the function of monitoring the voltage reset system. When the power supply voltage reaches the threshold voltage, the reset automatically pulls up to start the system.
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Page 17: Chapter 4 Hardware Introduction
FZ3 Deep Learning Accelerator Card Hardware Manual Chapter 4 Hardware Introduction 4.1 Interface summary Figure 4-1 Description Power input(12V/2A) DisplayPort （PS） Gigabyte Erthnet（PS） 1xUSB3.0 +1xUSB2.0（PS） PCIe x1（PS） TF Card（PS） BT1120 video input（PL） MIPI-CSI image input（PL） JTAG MicroUSB to UART debug port（PS）... -
Page 18: Ps Unit
FZ3 Deep Learning Accelerator Card Hardware Manual 4.2 PS Unit 4.2.1 DisplayPort One DisplayPort 1.2a interface, led from PS-side GTR, supports 4K / 30fps video output. The port is J6. 4.2.2 PCIe 1x One PCIe 1x interface, led from PS-side GTR, supports PCIe 2.1. The port is J5. -
Page 19: Unit
FZ3 Deep Learning Accelerator Card Hardware Manual 4.3 PL Unit 4.3.1 MIPI-CSI This development board has a MIPI-CSI interface on the PL end, and the MIPI signal directly passes through the IO on the PL end and enters the FPGA for decoding. For detailed IO details, please refer to the PINMAP. -
Page 20: Expansion Io
FZ3 Deep Learning Accelerator Card Hardware Manual Figure 4-3-2 4.3.3 Expansion IO This development board uses two 2x20PIN 2.54 pin headers for IO expansion, including 12V, 5V, 3.3V, 1.8V and other power output, CAN, RS485, USB2.0x2, 4xPSMIO, 40PIN PL terminal IO and other signals. The interfaces are J15 and J16. For the detailed signal definition and details, please refer to the schematic diagram and the ROUTE length form. -
Page 21: Other Interface
FZ3 Deep Learning Accelerator Card Hardware Manual 4.4 Other interface 4.4.1 Power input The power input interface of this development board defaults to 12V input, and the overcurrent protection is 2A. It is recommended to use 12V / 2A power input. The interface is J1. -
Page 22: Can
FZ3 Deep Learning Accelerator Card Hardware Manual 4.4.4 CAN This board has an CAN interface, and signals are drawn from pins 14 and 16 of interface J16. Figure 4-4-4 4.4.5 RS485 This development board has an RS485 interface, and signals are drawn from pins 8 and 10 of interface J16. -
Page 23: Chapter 5 Mechanical Parameters
FZ3 Deep Learning Accelerator Card Hardware Manual Chapter 5 Mechanical parameters Operating Temperature: -40~+85 ℃, Industrial grade(default) 0~+ 70 ℃, Commercial grade Humidity: 20%~90% Power Supply: 12V ( Limited support 6V-12.6V ) Expansion IO: Two 40pin 2.54 spacing dip connector ... -
Page 24: Appendix 1 Warranty & Technical Support Services
Delivery Time MYIR will always keep a certain stock for its regular products. If your order quantity is less than the amount of inventory, the delivery time would be within three days; if your order quantity is greater than the number of inventory, the delivery time would be always MYiR-Tech | www.myirtech.com... - Page 25 Technical Support MYIR has a professional technical support team. Customer can contact us by email (support@myirtech.com), we will try to reply you within 48 hours. For mass production and customized products, we will specify person to follow the case and ensure the smooth production.
- Page 26 6) For any maintenance service, customers should communicate with MYIR to confirm the issue first. MYIR’s support team will judge the failure to see if the goods need to be returned for repair service, we will issue you RMA number for return maintenance service after confirmation.
- Page 27 During the warranty period, the shipping cost which delivered to MYIR should be responsible by user; MYIR will pay for the return shipping cost to users when the product is repaired. If the warranty period is expired, all the shipping cost will be responsible by users.
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