CC Technical Documentation
RFConvClk (19.2 MHz digital)
The UPP distributes the 19.2 MHz Clk to the internal processors, the DSP, and MCU,
where the software multiplies this clock by seven for the DSP and by two for the MCU.
Issue 2 09/2005
Figure 4: RFCovCLk waveform
©2005 Nokia Corporation
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