Table 24 Gigabit Ethernet Signal Descriptions; Table 25 Intel ® High Definition Audio Link Signals Descriptions - Congatec COM Express conga-TS175 User Manual

Table 24 Gigabit Ethernet Signal Descriptions

Gigabit Pin # Description
Ethernet
GBE0_MDI0+ A13 Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate
GBE0_MDI0- A12 in 1000, 100, and 10Mb/sec modes. Some pairs are unused in some modes according to the following:
GBE0_MDI1+ A10
GBE0_MDI1- A9
MDI[0]+/-
GBE0_MDI2+ A7
MDI[1]+/-
GBE0_MDI2- A6
GBE0_MDI3+ A3 MDI[2]+/-
GBE0_MDI3- A2
MDI[3]+/-
GBE0_ACT# B2 Gigabit Ethernet Controller 0 activity indicator, active low.
GBE0_LINK# A8 Gigabit Ethernet Controller 0 link indicator, active low.
GBE0_LINK100# A4 Gigabit Ethernet Controller 0 100Mb/sec link indicator, active low.
GBE0_LINK1000# A5 Gigabit Ethernet Controller 0 1000Mb/sec link indicator, active low.
GBE0_CTREF A14 Reference voltage for Carrier Board Ethernet channel 0 magnetics center tap. The reference voltage is
determined by the requirements of the module PHY and may be as low as 0V and as high as 3.3V. The
reference voltage output shall be current limited on the module. In the case in which the reference is
shorted to ground, the current shall be limited to 250mA or less.
Note
1. The GBE0_LINK# output is not active during a 10 Mb connection. It is only active during a 100 Mb or 1 Gb connection. This is a limitation
of Ethernet Phy since it has only three LED outputs—ACT#, LINK100# and LINK1000#.
2. The GBE0_LINK# signal is a logic AND of the GBE0_LINK100# and GBE0_LINK1000# signals on the conga-TS175 module.
Table 25 Intel High Definition Audio Link Signals Descriptions
®
Signal Pin # Description
AC/HDA_RST# A30 Intel
®
external codec(s).
AC/HDA_SYNC A29 Intel
®
to the codec(s). It is also used to encode the stream number.
AC/HDA_BITCLK A32 Intel
®
data clock generated by the Intel
AC/HDA_SDOUT A33 Intel
®
output to the codec(s). This serial output is double-pumped for a bit rate of 48
Mb/s for Intel
Copyright © 2017 congatec AG
1000
B1_DA+/-
B1_DB+/-
B1_DC+/-
B1_DD+/-
High Definition Audio Reset: This signal is the master hardware reset to
High Definition Audio Sync: This signal is a 48 kHz fixed rate sample sync
High Definition Audio Bit Clock Output: This signal is a 24.000MHz serial
High Definition Audio controller.
®
High Definition Audio Serial Data Out: This signal is the serial TDM data
® High Definition Audio.
100 10
TX+/- TX+/-
RX+/- RX+/-
I/O
O 3.3VSB
O 3.3VSB
O 3.3VSB
O 3.3VSB
TSKLm16
I/O PU/PD Comment
I/O Twisted pair
Analog signals for
external
transformer.
O 3.3VSB
O 3.3VSB
O 3.3VSB
O 3.3VSB
Not
connected
PU/PD Comment
AC'97 codecs are not supported.
AC'97 codecs are not supported.
AC'97 codecs are not supported.
AC'97 codecs are not supported.
AC/HDA_SDOUT is a boot strap signal
(see note below)
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