Table of Contents
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SAL-1001 BOARD SCHEMATIC (16 OF 28)
1
A
2013/11/20 18:48
[ SKP_TU ]
YES
-
B
C8511
1000p
50V
X7R
C8601
4.7
10V
X7R
C8602
0.1
16V
X7R
C8603
0.1
16V
X7R
C8604
0.1
50V
X7R
C8605
0.047F
5.5V
C8606
0.1
50V
X7R
C
C8607
15p
50V
CH
C8608
15p
50V
CH
C8609
10
6.3V
X5R
C8610
0.1
50V
X7R
C8611
0.22
16V
X7R
C8612
0.1
50V
X7R
C8613
10
6.3V
D
X5R
C8614
XX
C8615
XX
C8616
1
10V
X5R
C8617
1
10V
X5R
C8618
XX
C8619
0.1
50V
X7R
E
C8620
XX
C8621
XX
C8622
XX
CL8508
CL8509
CL8510
CL8511
CL8512
CL8513
CL8514
CL8515
CL8516
CL8517
F
CL8518
CL8519
CL8520
CL8521
CL8522
CL8523
CL8526
CL8527
CN8501
40P
CN8502
10P
BLK
IC8501
TC74VCX541FK(EL)
IC8601
74AHCT1G125GW-12
IC8602
MM3376A50NRE
IC8603
TC74LCX573FT(EKJ
IC8604
BD8919FV-E2
Q8601
2SC4154TP-1EF
G
R1479
1k
1/10W
RN-CP
R8507
0
CHIP
R8508
0
CHIP
R8510
0
CHIP
R8512
0
CHIP
R8525
0
CHIP
R8526
0
CHIP
R8527
0
CHIP
H
R8528
0
CHIP
R8529
XX
R8530
XX
R8531
XX
R8532
XX
R8534
XX
R8535
XX
R8536
XX
R8537
XX
I
R8538
XX
J
K
L
A1
FMP-X10
2
3
4
5
6
Tuner Board I/F
NO
YES
NO
R8539
XX
XX
XX
R8540
10k
XX
1/16W
CHIP
XX
R8541
47
XX
1/16W
CHIP
XX
R8542
47
XX
1/16W
CHIP
*R8664
0
R8601
0
XX
1
TSI_CK
XX
0
CHIP
*RB8523
TSI_STRT
R8602
XX
XX
2
XX
3
TSI_EN
R8603
XX
XX
4
TSI_DAT
XX
5
R8604
0
XX
CHIP
6
XX
R8605
XX
XX
7
8
XX
R8607
XX
XX
*R8507
0
9
*R8508
0
R8609
0
XX
XX
10
CHIP
*R8510
0
R8610
10k
XX
11
*R8512
0
1/16W
XX
CHIP
12
R8612
XX
XX
13
XX
14
R8615
3.9k
XX
1/10W
*R8525
0
RN-CP
15
*R8526
0
XX
R8616
15k
XX
1/10W
16
RN-CP
*R8527
0
17
R8617
0
XX
*R8528
0
XX
CHIP
18
R8618
XX
XX
19
XX
20
R8619
0
XX
*R8673
0
CHIP
21
XX
R8620
2.2k
XX
22
1/10W
*R8675
0
RN-CP
XX
R8621
0
XX
23
*R8676
0
CHIP
24
R8622
100
XX
XX
1/10W
25
RN-CP
26
LNB_CONT
R8623
330
XX
1/10W
XX
RN-CP
X_SHORT_DET
27
R8624
100
XX
SYSTEM1_PWR
1/10W
28
RN-CP
XX
29
X_SYSTEM_RST
R8625
XX
XX
30
XX
R8626
XX
XX
31
+3.3V_MAIN
R8627
100
XX
32
XX
1/10W
RN-CP
33
R8628
100
XX
+3.3V_MAIN
1/10W
34
*VD8501
*VD8502
*VD8503
*VD8504
XX
RN-CP
35
R8629
0
XX
XX
CHIP
36
R8630
100
XX
STB5.8V
1/10W
37
XX
RN-CP
+12V_A
GND_D
38
XX
R8632
XX
XX
XX
39
STB5.8V
XX
R8633
XX
XX
+12V_A
40
XX
*CN8501
XX
R8634
XX
XX
XX
XX
R8635
0
XX
XX
CHIP
XX
R8644
XX
XX
XX
XX
R8653
XX
XX
XX
XX
R8654
0
XX
XX
CHIP
XX
R8655
1.5k
XX
1/10W
XX
RN-CP
XX
R8658
XX
XX
XX
R8659
10k
10k
XX
1/16W
1/16W
CHIP
CHIP
XX
R8660
XX
XX
XX
XX
R8661
10k
10k
1/16W
1/16W
XX
CHIP
CHIP
XX
R8662
0
XX
XX
CHIP
XX
R8663
XX
XX
XX
R8664
0
XX
CHIP
XX
R8667
0
XX
CHIP
XX
R8668
22
XX
1/16W
*C8604
CHIP
0.1
XX
R8669
22
XX
*IC8603
1/16W
CHIP
OE
VCC
XX
R8670
10k
10k
1/16W
1/16W
CHIP
CHIP
1D
1Q
XX
R8671
10k
10k
1/16W
1/16W
CHIP
CHIP
2D
2Q
XX
R8672
XX
XX
SCI_CLKDIV
*R8669
22
TSIO_DAT_3
3D
3Q
XX
R8673
0
XX
CHIP
*R8660
DIV_SKP
XX
DIV_SKP
4D
4Q
XX
R8674
10k
XX
*R8661
1/16W
*R8671
CHIP
10k
10k
XX
R8675
0
XX
5D
5Q
CHIP
XRST_SKP
+3.3V_MAIN
+3.3V_MAIN
XX
R8676
0
XX
6D
6Q
CHIP
*R8670
7D
7Q
XX
RB8503
XX
XX
*R8659
10k
10k
RB8505
XX
XX
*R8658
XX
CMDVCC_SKP
CMDVCC_SKP
8D
8Q
XX
RB8506
XX
XX
RB8508
47
XX
*R8668
22
TSIO_DAT_2
GND
LE
XX
RB8509
47
XX
RB8523
0
XX
SCI_CMDVCC
*R8609
0
XX
VD8501
XX
XX
GND_D
VD8502
XX
XX
XX
VD8503
XX
XX
VD8504
XX
XX
XX
X8601
16MHz
XX
X_SOC_RST
+5V_BCAS
SCI_DIO
TSIO_STRT
*R8601
0
CI_DT[3]
*R8602
XX
CI_RST
*R8603
*R8672
XX
XX
SCI_RST
TSIO_EN
*R8662
0
+5V_BCAS
GND_D
*IC8601
CI_DT[2]
_G
VCC
*R8604
0
IN A
GND
OUT Y
*R8612
XX
*R8610
10k
*C8603
0.1
GND_D
From/To AYU2
X_SCI_DET
TSIO_DAT_1
STB5.8V
150mA
+5V_BCAS
5V REG
*IC8602
VIN
VOUT
*C8621
GND
*R8667
XX
0
*R8615
SYSTEM3_PWR
CE
NC
*C8619
0.1
*C8622
*C8601
*C8602
XX
4.7
0.1
*C8605
0.047F
GND_D
7
8
9
10
*R8644
XX
*CL8516
TSIO_CK
*RB8503
XX
*CL8517
TSIO_STRT
*CL8518
TSIO_EN
1
*CL8521
XX
*RB8506
TSIO_DAT_2
*CL8520
TSIO_DAT_1
*CL8519
TSIO_DAT_0
*CL8522
TSIO_DAT_3
*CL8523
R8677
XX
To IC8501
TSIO_DAT_7
I2C_CCP_SCL
I2C_CCP_SDA
*CL8509
I2CB_SCL
CI_OINT
9_5F
*CL8508
I2CB_SDA
TU_ID
5_3E/5_7E
*CL8526
SPID_DI
12H
*CL8527
SPID_CK
12I
SPIC_DO
*CL8511
SPIC_DI
C
C
P
_
I
N
T
1
2
J
*CL8510
SPIC_CS
PICTURE_MUTE_INT
12J
CL8528
SPIC_CK
CI_RST
CL8529
CI_DT[3]
CL8530
CI_DT[2]
TSIO_DAT_5 =TS_PI_DAT_5
=POL_SW
TSIO_DAT_5
SYSTEM4_PWR
2
TSIO_DAT_4
TSIO_DAT_4 = TU_XRST
TSIO_DAT_6
TSIO_DAT_6 = TU_OSCEN
B
+3.3V_MAIN
+3.3V_MAIN
*R8529
XX
*R8530
XX
*R8531
XX
*R8532
XX
671149701
*C8511
1000p
*IC8501
GND_D
/OE1
VCC
GND_D
A1
/OE2
8C
TSI_CK
A2
Y1
*R8541
47
A_TSI_CK
11D
A_TSI_DAT
11D
To AYU2
8D
TSI_EN
A3
Y2
A_TSI_STRT
11D
A4
Y3
A_TSI_EN
11E
8D
TSI_STRT
A5
Y4
*RB8508 47
*R8542
47
LY_TSI_CK
41_9C
*RB8509 47
A6
Y5
LY_TSI_DAT
41_9C
To LYON
TSI_DAT
8D
A7
Y6
LY_TSI_STRT
41_9C
A8
Y7
LY_TSI_EN
41_9C
GND
Y8
GND_D
*R8534
XX
*R8535
XX
B
*R8536
XX
*R8538
XX
*C8607
15p
1
BD8919FV-E2
*IC8604
*C8608
15p
XTAL1
GND
2
*R8627
100
GND_D
XTAL2
CMDVCCB
*R8620
*R8628
GND_D
2.2k
100
*C8610
VDD
OFFB
*C8609
0.1
10
CLKSEL
PRES
+5V_BCAS
*R8622
100
RSTIN
VDDP
*R8623
330
IO_U
VCC
*R8624
*R8630
100
100
*C8611
*C8612
*C8613
0.22
0.1
10
C_GND
CLK
GND_D
IO_C
RST
*R8655
671649701
GND_D
1.5k
*R1479
1k
*R8629
0
*R8621
*R8617
+3.3V_MAIN
0
0
*R8618
XX
*R8635
0
*R8619
0
*R8663
XX
*C8617
*C8616
1
1
*Q8601
3.9k
*C8606
0.1
*R8616
15k
SECTION 4 - DIAGRAMS
11
12
13
14
47
R8585
9_8D
TSIO_CK
RB8514
47
SCI_RESET
9_8D
TSIO_EN
SCI_DIO
9_8D
TSIO_STRT
To BCAS Connector
9_8K
TSIO_DAT_2
SCI_CMDVCC
9_8K
TSIO_DAT_1
RB8510
47
9_8D
TSIO_DAT_0
SCI_CLKDIV
9_8K
TSIO_DAT_3
9_8K/6_2B
TSIO_DAT_5
*** Strap Setting ***
8C/6_2B
TSIO_DAT_4
TSIO_DAT_4 = STRAP_G[16](InternalPD)
RB8511
TSIO_DAT_5 = STRAP_G[17](InternalPD)
47
8C/6_2B
TSIO_DAT_7
TSIO_DAT_6 = STRAP_G[18](InternalPD)
TSIO_DAT_7 = STRAP_G[19](InternalPD)
8C/6_2B
TSIO_DAT_6
FLASH Device detection
1
R8548
47
10F
A_TSI_CK
RB8512
A_TSI_DAT
47
10F
A_TSI_STRT
10F
A_TSI_EN
10F
R8549
47
RB8513
47
+3.3V_MAIN
*** Strap Setting ***
DAUOA_DAT_0 = STRAP_G[5](InternalPD)
FEIP ES EVA mode (for TSB use)
0:default pin assign
BROWNIE / D-AMP2
1:FEIP_GPIO pin assign
I2CE
CL8507
DAUOC_LRCK
= STRAP_G[6](InternalPD)
6E/24_2G
I2C_CCP_SDA
DAUOC_BCK
= STRAP_G[7](InternalPD)
CL8506
->Strap setting at PERI(STBY)
6E/24_2G
I2C_CCP_SCL
DAUOC_DAT_0 = STRAP_G[8](InternalPD)
ETHER REFCLK FREQUENCY
0:50MHz
0:25MHz
+3.3V_MAIN
EPP
RB8521
DAUOC_MCLK_CLK
DAUOA_DAT0_HSS1
47
24_5E
R8505
DAUOC_BCK_CLK
6F/5_15B
DAUOC_LRCK_CLK
6F/5_15B
+3.3V_MAIN
DAUOC_DAT_0
DAUOD_MCLK_CLK
R8513
*** Strap Setting ***
DAUOD_LRCK
= STRAP_G[9](InternalPD)
DAUOD_BCK
= STRAP_G[10](InternalPD)
DAUOD_LRCK_CLK
DAUOD_DAT_0
= STRAP_G[11](InternalPD)
DAUOD_BCK_CLK
DAUO_SPDIF_0 = STRAP_G[12](InternalPD)
R8514
DAUOD_DAT_0
For Ryu SW and DDR3 4GB
PCBID = b'1001
R8515
DAUO_SPDIFOP_HSS
DAUO_SPDIFOP_HSS
R8516
*** Strap Setting ***
SPIC_CK = STRAP_G[20](InternalPD)
(10/14)
->RESERVED for software use
R8518
+3.3V_MAIN
SPIC_DO = STRAP_G[21](InternalPD)
->JIG MODE Setting
R8519
SPID_CK = STRAP_G[22](InternalPD)
GND_D
0:debug_mode_off
1:debug_mode_on
6G
SPIC_DO
6G
SPIC_DI
6H
SPIC_CK
6H
SPIC_CS
RB8522
6H
SPID_DI
6H
SPID_CK
GND_D
(10/14)
*** Strap Setting ***
GPIO_5
= STRAP_G[0] (InternalPD)
GPIO_63 = STRAP_G[1] (InternalPD)
+3.3V_MAIN
GPIO_64 = STRAP_G[2] (InternalPD)
STRAP_G[1:0] = 00 CKG_PLL_HCPU_M=10'd200
STRAP_G[1:0] = 01 CKG_PLL_HCPU_M=10'd180
STRAP_G[1:0] = 10 CKG_PLL_HCPU_M=10'd160
STRAP_G[1:0] = 11 CKG_PLL_HCPU_M=10'd140
STRAP_G[2] = 0 ETHER_REF_CLK output mode
GND_D
STRAP_G[2] = 1 ETHER_REF_CLK
input mode
CCP_INT
PICTURE_MUTE_INT
GND_D
CI_OINT
VFE digital :
*R8653
XX
CAS
Please put VFE bus on Layer-3 for EMI/interfarence C/M.
R8570-R8576:
if possible on PWB design, please put close to Brownie(IC9001).
*CN8502
PRES
IO
VCC
RST
CLK
-
6
X
'
.
.
-
5
X
'
.
.
-
4
X
'
.
.
-
3
X
'
.
.
-
2
X
'
.
.
-
TS
1
X
1
'
13
.
12
.
18
GND_D
HISTORY
SUFFIX
ECN-NO.
R E V I S I O N
X COUNT
REPL.
D A T E
DRAWN BY
PLANNED BY
CHECKED BY
APPROVED BY
MODEL
PART NO.
ALL resistors are in ohms,W unless otherwise noted.
ALL capacitors are in uF(p:pF)unless otherwise noted.
THIS DOCUMENT IS THE PROPRIETARY PROPERTY OF SONY. ITS USE IS AUTHORIZED ONLY FOR RESPONDING TO A REQUEST FOR QUOTATION, OR FOR THE PERFORMANCE OF WORK FOR SONY. ALL QUESTIONS MUST BE REFERRED
TO THE LOCAL PURCHASING DEPARTMENT OF SONY. THE REPRODUCTION, DISTRIBUTION AND UTILIZATION OF THIS DOCUMENT AS WELL AS THE COMMUNICATION OF ITS CONTENTS TO OTHERS WITHOUT EXPRESS AUTHORIZATION
IS PROHIBITED. OFFENDERS WILL BE HELD LIABLE FOR THE PAYMENT OF DAMAGES. ALL RIGHTS RESERVED IN THE EVENT OF THE GRANT OF A PATENT, UTILITY MODEL OR DESIGN. COPYRIGHT RESERVED.
ISSUED '
.
.
15
16
A
2013/11/20 18:48
[ SOC ]
240
240AVS
IC9000
CXD4741GB
CXD4741GB-1
AYU2
B
TSIO
AP10
TSIO_CK/GPIO_52/SCI_CK/SCI_TDA_CLK
AM10
TSIO_EN/GPIO_53/SCI_RST/SCI_RST
AN10
TSIO_STRT/GPIO_54/SCI_DI/SCI_DIO
AP11
TSIO_DAT_0/GPIO_55/SCI_DOEN
AN11
TSIO_DAT_1/GPIO_56/SCI_DET/SCI_DET
C
AM11
TSIO_DAT_2/GPIO_57/SCI_VEN/SCI_CMDVCC
AP12
TSIO_DAT_3/GPIO_58/SCI_OCD/SCI_CLKDIV
AN12
TSIO_DAT_4/GPIO_59
AM12
TSIO_DAT_5/GPIO_60
AP13
TSIO_DAT_6/GPIO_61
AN13
TSIO_DAT_7/GPIO_62
AP15
TSI_CK
AN15
TSI_EN
AM15
TSI_STRT
AP16
TSI_DAT
D
AM13
TSIE_CK
AP14
TSIE_EN
AN14
TSIE_STRT
AM14
TSIE_DAT
*IC9000
CXD4741GB
E
AYU2-BROWNIF_I/F
AM9
I2C_CCP_SDA
AP8
I2C_CCP_SCL
F
AN20
DAUOC_MCK
47k
AP20
DAUOC_BCK
AM19
For HP/Line Out
DAUOC_LRCK
AN19
DAUOC_DAT_0
AP19
DAUOD_MCK
47k
AN18
DAUOD_BCK
AM18
For SCART Out
DAUOD_LRCK
AP18
DAUOD_DAT_0
AM16
DAUIA_BCK
47k
AP17
For Analog Input
47k
DAUIA_LRCK
G
AN16
DAUIA_DAT_0
47k
AN17
X_ADAC_MUTEC
47k
AM17
Brownie Audio DAC Mute
47k
X_ADAC_MUTED
AP31
SPIC_DO
AN31
SPIC_DI
For CI Transfer
AP30
SPIC_CS
AM30
SPIC_CK
47
AN30
SPID_DI
Slice Data from Brownie
H
AL29
SPID_CK
(10/14)
AM22
R8517
47k
VFE_DIO_CLK
AN22
VFE_DIO_DEN
R8647
47k
AP22
VFE_DIO_D9_4
R8648
47k
SD Video
AM21
VFE_DIO_D8_3
AYU2 -> Brownie :
R8649
47k
AN21
Brownie -> AYU2 :
R8650
47k
VFE_DIO_D7_2
AP21
VFE_DIO_D6_1
R8651
47k
AM20
VFE_DIO_D5_0
R8652
47k
I
AM23
CCP_INT/GPIO_64
AN23
PICTURE_MUTE_INT/GPIO_5
AN8
X_AUDIO_MUTEC
C : SP/HP Out Mute
R8522
47k
AM8
D : SCART Out Mute
X_AUDIO_MUTED
R8523
47k
AP23
CI_OINT/GPIO_63
*IC9000
CXD4741GB
J
UNIT
TOLERANCE
USED ON
RANK
mm
ANGLE
FAMILY
K
SCALE
:
ORIGINAL
SAL BOARD
MODEL
MATERIAL(COLOR)
FINISH(COLOR)
DESCRIPTION
(E)
SIGN.
AY STREAM
(J)
PART NO.
SHEET
L
PROTO
17/29
52
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