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Run Self-Test
The self-test checks the integrity of the internal operation of the electron-
ic components by performing memory tests and by sending and verify-
ing data test patterns through all internal interfaces. Although actual
user data cannot be passed during these tests, the self-test can be run
with the network and DTE interfaces in place and will not disturb any
external interface.
The memory portion of the self-test automatically executes upon power-
up. A full self-test can be commanded from a front panel menu or from
T-Watch PRO.
In addition to the specified self-tests, background tests are run on vari-
ous parts of the internal electronics. These run during normal operation
to confirm continued correct functioning.
This menu selection is used to execute a full internal self-test. The results
of the self-tests are displayed in the LCD. Upon invoking the command,
the LCD displays System Self-Test and the Test LEDs are illuminated.
Test failures are displayed in the LCD window. The self-test consists of
the following tests:
Board level tests
Each of the TSU 600 boards contain an on- board processor which exe-
cutes a series of tests checking the circuitry on the board.
• RAM tests; EPROM checksum
• DS0 map tests
• On-board data path; sending a known test pattern through an on-
board loop
Unit level tests
• Front panel LED verification
• Phase Lock Loop verify
• Board-to-board interface test
A test pattern is sent from the controller through a loopback on all other
boards and is checked on the controller. This verifies the data path,
clocks, and control signals.
If a failure is detected, note the failure number and contact ADTRAN
Technical Support.
The execution of self-test will disrupt normal data flow and prevent re-
mote communication until the self-test is completed.
61202076L1-1
TSU 600 User Manual
Chapter 7. Test Menu
7-7
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