Logical - Xilinx System Generator V2.1 Reference Manual

Xilinx System Generator v2.1 Reference Guide
Block Parameters Dialog Box
The block parameters dialog box can be invoked by double-clicking the icon in your
Simulink model.
Figure 3-57: Inverter block parameters dialog box
Parameters used by this block are explained in the Common Parameters section of the
previous chapter of the Reference Guide.
Xilinx LogiCORE
The Inverter block uses the Xilinx LogiCORE Bus Gate V5.0 if the Implement with
Xilinx Smart-IP Core parameter is checked and the input data width is between
1 and 64, inclusive. Otherwise, the block is implemented as a synthesizable VHDL
module.
The Core datasheet can be found on your local disk at:
%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do
c\bus_gate.pdf

Logical

logic optimization can be applied during synthesis and mapping.
86
The Xilinx Logical block performs a bit-wise logical operation on 2,
3, or 4 fixed point numbers. Operands are aligned at their respective
binary points, zero padded, and sign extended as necessary. The
logical operation is performed and produced at the output port.
The block can be implemented either as a Xilinx LogiCORE or as a
synthesizable VHDL module. If you build a tree of logical gates, it is
typically better to choose the synthesizable implementation so that
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