Delay - Xilinx System Generator V2.1 Reference Manual

Xilinx LogiCORE
The block always uses the Xilinx LogiCORE: Binary Counter V5.0.
The Core datasheet can be found on your local disk at:
%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do
c\binary_counter.pdf

Delay

latency of 1, and contains an Initial Value parameter. The Delay block supports a user
specified latency, but no initial value, other than zeroes.
Block Parameters Dialog Box
The block parameters dialog box can be invoked by double-clicking the icon in your
Simulink model.
Figure 3-9: Delay block parameters dialog box
Parameters specific to this block are:
Other parameters used by this block are explained in the Common Parameters section
of the previous chapter.
The Delay block does not use a Xilinx LogiCORE, but is efficiently mapped to utilize
the SRL16 feature of Xilinx devices.
Basic Elements
The Xilinx Delay block is a delay line (also called a shift register) of
configurable length, allowing you to add latency to your design. Data
presented at the input will appear at the output after a user specified
number of sample periods.
The Delay block differs from the Register in that the Register allows only
Initialize with Zeros: The block's internal registers are set to zero if this
option is selected, otherwise the output will be NaN (Not a Number) until the
registers are flushed. For example, if the Delay block has a latency of 5 and this
option is selected, the first five output values will be zeros. If this option is not
selected, the first five output values will be NaN.
Latency: You may set the amount of latency in the Latency field.
Xilinx Blocks
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