Xilinx System Generator V2.1 Reference Manual page 122

Xilinx inc. portable generator user manual
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Xilinx System Generator v2.1 Reference Guide
The number of bits used to implement a registered mealy state machine is given by
the equations:
where
The following table gives examples of Block RAM sizes necessary for various state
machines:
Number of States
The block RAM width and depth limitations are described in the online help for the
Single Port RAM block.
Xilinx LogiCORE
This block uses Version 3.2 of the Xilinx Single Port Block Memory LogiCORE.
The Core datasheet for the Single Port Block Memory may be found locally at:
%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\blkmemsp_v3_2\do
c\sp_block_mem.pdf
122
depth
=
width
N
=
depth width
N = total number of block RAM bits
k =
log
s
2
s = number of states
i = number of input bits
o = number of output bits
Number of
2
4
8
16
32
52
100
k
i
k
+
i
2
2
=
2
=
k
+
o
k
+
=
k
+
o
2
Number of
Input Bits
Output Bits
5
1
6
5
4
1
4
i
Block RAM Bits
Needed
10
704
2
32
7
5120
4
4096
3
4096
11
2176
5
24576
Xilinx Development System

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