HP 13255 Technical Information page 24

132~5
Cartrldge Tape Module
13255-91032/22
Bev AUG-01-76
while reading in data, transitions detected are handled in the same
manner as when reading the preamble except for transitions occuring
in the data zone. In this case,
RD
DATA Is shifted right into the
serial data register and bit counter is incremented. When the last
bit is decoded, the data
I/O
buffer Is parallel loaded from the serial
d~ta
register (shifted right one bit), BYTE ROY is set, and the process
is repeated tor the next byte. The data in the
I/O
buffer must be read
(which clear 8YT~ ROY) before the next byte is decoded In order to
avoid 10s1no data.
3.0.5
HOLE
OlT~rt
LOGIC - CTU
INT~RFAC~
PCA.
3.0.5.1 This circuitry detects the presence of a hole in the tape of either CTU
Transport Assembly (depending on which transport is selected) and gen-
erates the
DHOL, DHOL DET,
and
USO
signals.
3.0.5.2 The Read/Write peA provides the signals HOLO and HOLl that indicate the
presence of a hole on unit 0 or unit 1,
res~ectlvely
when the signal Is
low. When Unit
1
is selected and a hole is detected, U22, Pin
11
will
be high. When Unit
0
is selected,
USO
at U35, Pin
4
is high,
a
hole is
detected, and U22, Pin
8
is high. Pins
8
and
11
of U22 are wire ORed
into U28, Pin 6 where they
ar~
synchronized to
s~s
eLK and provide the
DHOL
signal at U28, Pin
7.
DHOt at U29, Pin
4
is exclusive-ORed with
DHOL delayed by one cycle ot SYS CLK at U29, Pin 5 and Qenerates the
DHOL DET siqnal which provides a pulse wnen a hole is initially de-
tected and another pulse when it Is no longer detected. It should be
noted that DHOL and DHOL DET are ANDed in the command logic to provide
a single pulse when a hole is inItially detected.
3.0.6 TACH LUGIC - CTU INTtRFACE PCA.
3.0.6.1 The tach logic divides the TACH signal from the Read/Write PCA by a
factor Of two and uses the resulting signal to generate the signals
TACH/2 and DTACH/2.
3.0.6.2 The TACH signal is used as the ClOCK input for U~6, which Is configured
as a T flip-flop, and results in one transition of the signal at U26,
Pin 6 for every two transitions of the TACH signal. U28 synchronizes
the signal from U26, Pin 6 with the SYS CLK and generates the TACH/2