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TP1
L1
F-BEAD 1.4A
3V3
VLOGIC
Y E L L O
W
R1
+
680
10uF,50V
C1
POWER
LED11
+
68uF 16V
C3
TP3
VDD
R10
2k
POWER
TP8
TP9
TP10
LED12
+
C7
.1uF, 50V
C6
22uF,50V
U3
20
RXD0
TP4
TXD
1
DTR#
2
RTS#
VCC3O
3
VCCIO
TXD0
4
TP6
RXD
5
10
RI#
CBUS2
6
17
GND
CBUS1
7
15
DSR#
VCC
8
14
DCD#
RESET#
9
16
CTS#
GND
19
13
CBUS3
3V3OUT
18
12
USBDM
CBUS0
USBDM
11
USBDP
USBDP
FT231XS-R
* *
FB1
1
2
M
I N I - U S B
FERRITE BEAD
* *
J8
USB_MINI_B_0
C22
10nF
1
VCC
R35
27R
2
D-
3
D+
R36
27R
4
C26
NC
5
C25
47pF
GND
6
47pF
CASE
QSG‐8428‐R Rev. A
U4
80
MISO2
79
MOSI2
78
SCK2
14
SCK
IOC7/PT7
13
SI
C2
IOC6/PT6
12
IOC5/PT5
11
.1uF
SEL
IOC4/PT4
8
SO
IOC3/PT3
7
nCS
IOC2/PT2
6
IOC1/PT1
5
SO1
IOC0/PT0
75
PM0/RX
74
PM1/TX
BKGD
15
MODC/BKGD
VLOGIC
69
PJ6
68
PJ7
66
R13
R14
PS3/TXD1
65
PS2/RXD1
64
10k
10k
TXD0
PS1/TXD0
63
RXD0
PS0/RXD0
40
XIRQ/PE0
39
IRQ/PE1
PE2
38
PE2
PE3
37
PE3
PE4
27
ECLK/PE4
PE5
26
PE5
25
PE6
24
TP7
XCLKS/PE7
S E N S E
T R I G G E R
C8
10pF
34
1 Mohm
EXTAL
R22
C13
Y 1
10pF
35
XTAL
4MHz
5V
31
C14
VDDPLL
.1uF
C15
C17
C16
R32
.01uF
220nF
33
VCC3O
470pF
4.7K 1%
VSSPLL
C21
32
XFC
C20
220nF
0.1uF
MC9S12XDT512CAA
5V
VLOGIC
R33
3.3K
USBDM
J9
BKGD
1
2
USBDP
3
4
nRESET
5
6
HEADER 2X3
D E B U G
H D R
HOLT INTEGRATED CIRCUITS
1
SS1/PP3
2
SCK1/PP2
3
MOSI1/PP1
4
MISO1/PP0
30
nRESET
RESET
70
SCK0
71
MOSI0
72
SS0
73
MISO0
J1
16
PB0
17
VLOGIC
PB1
18
PB2
19
PB3
20
PB4
21
B A N K
U 1
R E D
PB5
22
B A N K
U 2
R E D
LED9
PB6
23
R38
LED10
680
PB7
680
41
LED1
PA0
42
G R N
LED2
R12
680
PA1
43
680
LED3
PA2
44
LED4
R16
680
PA3
45
680
LED5
PA4
46
LED6
R18
680
PA5
47
680
LED7
PA6
48
LED8
R20
680
PA7
680
51
PAD00/AN00
52
PAD01/AN01
53
PAD02/AN02
54
PAN03/AN03
55
PAD04/AN04
56
PAD05/AN05
57
PAD06/AN06
58
PAD07/AN07
29
VLOGIC
VDDR1
77
VDDX
C9
C10
U2_VLOGIC
220nF
220nF
28
VSSR1
76
VSSX
62
VSSA
67
U2_VDD
VLOGIC
VREGEN
59
VDDA
60
VRH
61
VRL
9
VDD1
49
C19
VDD2
C18
10
220nF
220nF
VSS1
50
VSS2
36
TEST
VLOGIC
VLOGIC
C23
.1uF
S P I
B O
A R D
INTERFACE
J10
SW4
R E S E T
MICRO
15
U1
SO1
9
8
R9
SO
SENSE8
SCK
10
7
R8
SCK
SENSE7
11
6
nCS
R7
CS
SENSE6
12
5
SI
R6
SI
SENSE5
13
4
SEL
R5
SEL
SENSE4
14
3
R4
VLOGIC
SENSE3
15
2
R3
GND
SENSE2
16
1
R2
VDD
SENSE1
C4
.1uF
.1uF
8428 SO16
C5
R37
J2
J3
U1_VDD
R11
R15
R17
R19
VSENSE 1
U2
9
8
SO
R30
SO
SENSE8
10
7
SCK
R29
SCK
SENSE7
11
6
nCS
R28
CS
SENSE6
12
5
R27
SI
SENSE5
13
4
SEL
R26
SEL
SENSE4
14
3
R25
VLOGIC
SENSE3
15
2
R24
GND
SENSE2
16
1
C11
R23
VDD
SENSE1
.1uF
C12
J13
8428 SO16
.1uF
J12
J6
SW3
U P
=
O
P E N
( H I G
H )
VSENSE 2
N o t e s :
1. There should be no traces under the SENSE[1:8] lines
R34
220K
nRESET
of U1 and U2 to prevent inductive pick up during the lighting test, this
incudes the GND and power planes
C24
J11
T i t l e
.1uF
HI-8428 -R, 8 Input Discrete with SPI - Engineering Board
" H O
L D
I N
RESET"
GND
S i z e
D o c u m
e n t
N u m
b e r
B
<Doc>
D a t e :
Thursday , September 18, 2014
Oct 2014
J4
9
8
3k
7
3k
6
3k
5
3k
4
3k
3
3k
2
3k
1
3k
SW1
O
N
( C L O
S E D )
1
2
3
4
5
6
7
8
1
2
3
V S E N S E
B A N K
U 1
TP2
J7
9
8
3k
7
3k
6
3k
5
3k
4
3k
3
3k
2
3k
1
3k
SW2
O
N
( C L O
S E D )
1
2
3
4
5
6
7
8
1
2
3
V S E N S E
B A N K
U 2
TP5
R e v
<Rev Code>
S h e e t
o f
1
4
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