Page 1
Vodafone Chair Mobile Communications Systems, Prof. Dr.-Ing. G. Fettweis Digital Signal Transmission Lab SS 08 Oliver Arnold Steffen Kunze...
Page 2
Introduction Hardware Why to use digital signal processing? General introduction to DSPs The TMS320C6711 DSP Architecture Overview Peripherals DSK6711 evaluation board - Software Code Composer Studio DSP/BIOS Multi-channel Buffered Serial Port (McBSP) TU Dresden, 4/29/2008 chair Slide 2...
Page 3
chair Hardware TU Dresden, 4/29/2008 Slide 3...
Page 4
Digital Signal Processing (DSP) Wireless / Cellular Voice-band audio RF codecs Voltage regulation Consumer Audio Stereo A/D, D/A Mixers Multimedia Stereo audio Imaging Graphics palette Voltage regulation TU Dresden, 4/29/2008 PRML read channel MR pre-amp Servo control SCSI tranceivers DSP: Technology Enabler DTAD...
System Considerations Interfacing Interfacing Size Size Ease of Use Ease of Use • • Programming Programming • • Interfacing Interfacing • • Debugging Debugging TU Dresden, 4/29/2008 Performance Performance Cost Cost • • Device cost Device cost • • System cost System cost •...
Page 6
Why Go Digital? Digital signal processing techniques are now so powerful that sometimes it is extremely difficult, if not impossible, for analogue signal processing to achieve similar performance. Examples: FIR filter with linear phase Adaptive filters TU Dresden, 4/29/2008 chair Slide 6...
Page 7
Why Go Digital? Analogue signal processing is achieved by using analogue components such as: Resistors Capacitors Inductors The inherent tolerances associated with these components, temperature, voltage changes and mechanical vibrations can dramatically affect the effectiveness of the analogue circuitry TU Dresden, 4/29/2008 chair Slide 7...
Page 8
Why Go Digital? With DSP? - It is easy to: Change applications Correct applications Update applications Additionally DSPs reduce: Noise susceptibility Chip count Development time Cost Power consumption TU Dresden, 4/29/2008 chair Slide 8...
Page 9
chair General Introduction to DSPs TU Dresden, 4/29/2008 Slide 9...
Page 10
What Problem Are We Trying To Solve? chair Digital sampling of Most DSP algorithms can be an analog signal: expressed as: count Σ i = 1 for (i = 1; i < count; i++){ sum += m[i] * n[i]; } TU Dresden, 4/29/2008 Slide 10...
Page 11
What are the typical DSP algorithms? The Sum of Products (SOP) is the key element in most DSP algorithms: Algorithm Finite Impulse Response Filter Infinite Impulse Response Filter Convolution Discrete Fourier Transform Discrete Cosine Transform TU Dresden, 4/29/2008 Equation ∑ a x n k ∑...
Page 12
Why do we need DSP processors? Use a DSP processor when the following are required: Cost saving Smaller size Low power consumption Processing of many “high” frequency signals in real-time Use a GPP processor when the following are required: Large memory Advanced operating systems TU Dresden, 4/29/2008 chair...
Page 13
Hardware vs. Microcode multiplication DSP processors are optimized to perform multiplication and addition operations. Multiplication and addition are done in hardware and in one cycle. Example: 4-bit multiply (unsigned). Hardware Hardware x 1110 x 1110 10011010 10011010 TU Dresden, 4/29/2008 Microcode Microcode 1011...
Page 14
General Purpose DSP vs. DSP in ASIC Application Specific Integrated Circuits (ASICs) are semiconductors designed for dedicated functions. The advantages and disadvantages of using ASICs are listed below: Advantages Advantages • High throughput • High throughput • Lower silicon area •...
Page 15
Floating vs. Fixed point processors Applications which require: High precision Wide dynamic range High signal-to-noise ratio Ease of use Need a floating point processor Drawback of floating point processors: Higher power consumption Usually higher cost Usually slower than fixed-point counterparts and larger in size TU Dresden, 4/29/2008 chair...
General DSP System Block Diagram External Memory TU Dresden, 4/29/2008 Internal Memory Internal Buses Central Processing Unit chair Slide 17...
Page 18
‘6711 CPU Overview Specification Clock Rate: 100/150 MHz 0.18-μm/5-Level Metal Process – CMOS Technology CPU has got two Datapaths, Four ALUs (Floating- and Fixed-Point) Two ALUs (Fixed-Point) Two Multipliers (Floating- and Fixed-Point) Load-Store Architecture 2*16 32-Bit General-Purpose Registers TU Dresden, 4/29/2008 600/900 MFLOPS altogether: chair...
Page 19
‘6711 CPU Overview VelociTI advanced very-long instruction words (VLIW) Program Memory Width is 256 Bit Up to 8 32-Bit instructions can be executed in parallel/Cycle 16, 32 and 40 bit fixed point operands 32 and 64 bit floating point operands Instruction parallelism is detected at compile-time no data dependency checking is done in Hardware.
Page 20
Functional Block and CPU Diagram chair TU Dresden, 4/29/2008 Slide 20...
Page 21
A ‘6711 Datapath .S & .L Arithmetic, Logical & Branch functions Multiply, Rotation, Bit expansion Data-addressing Only way to access memory Cross path TU Dresden, 4/29/2008 chair Slide 21...
Page 22
Functional Units and Operations Performed chair TU Dresden, 4/29/2008 Slide 22...
Page 24
'C6x System Block Diagram Addr Addr D (32) D (32) EMIF EMIF ’ ’ Memory Memory Sync Sync Async Async TU Dresden, 4/29/2008 Program Program Data Ram Data Ram Internal Buses Internal Buses Control Regs Control Regs chair Serial Port Serial Port Host Port Host Port...
Page 25
‘C6000 Internal Buses Internal Memory External Memory Peripherals TU Dresden, 4/29/2008 Program Addr Program Data Data Addr - T1 Data Data - T1 Data Addr - T2 Data Data - T2 DMA Addr - Read DMA Data - Read DMA Addr - Write DMA Data - Write chair x256...
Page 26
How are Peripherals Controlled? Control and configuration of internal peripherals is done by memory mapped control registers There is a separate memory mapped register file of control registers Example of Timer mode control register: Rsvd TU Dresden, 4/29/2008 TSAT Rsvd PWID DATIN INVIMP...
Memory Map 0000_0000 64KB Internal (Progam or Data) 0180_0000 On-chip Periph 8000_0000 256MB External 9000_0000 256MB External A000_0000 256MB External B000_0000 256MB External FFFF_FFFF TU Dresden, 4/29/2008 16MB SDRAM 128K byte FLASH 4 byte I/O Port Available via Daughter Card Connector chair 9008_0000...
Page 29
Operands Operands can be 5-bit constants (or 16-bit in some special instruct.) 32-bit Registers 40-bit Registers 64-bit Registers A 40-bit or a 64-bit register can be obtained by concatenating two registers The registers must be from the same side The first register must be even and the second odd (e.g. A1:A0, B9:B8 or A15:A14) The registers must be consecutive TU Dresden, 4/29/2008...
Conditional execution All instructions in each Functional Unit of both Data paths can be executed conditionally Only the Registers A1, A2, B0, B1, B2 can hold the condition Conditional Execution uses the Syntax [!condition] [!B0] ADD.L1 [B0] ADD.L1 TU Dresden, 4/29/2008 Instruction A1,A2,A3 ;...
Page 31
Branches Branches are required to realize loops and change the program flow Branches are very useful in conjunction with conditional execution There are two branch types supported: Relative Branching Absolute Branching TU Dresden, 4/29/2008 chair Slide 31...
Page 32
More on the Branch Instruction (1) With this processor all the instructions are encoded in a 32-bit. Therefore the label must have a dynamic range of less than 32-bit as the instruction B has to be coded. Case 1: Relative branch. Label limited to +/- 2 TU Dresden, 4/29/2008 bit relative address...
Page 33
More on the Branch Instruction (2) By specifying a register as an operand instead of a label, it is possible to have an absolute branch. This will allow a dynamic range of 2 Case 2: Case 2: Absolute branch. Absolute branch. Operates on .S2 ONLY! Operates on .S2 ONLY! TU Dresden, 4/29/2008...
Page 34
Getting Data from the Memory All Instructions work exclusively on Registers The .D Units in the Data-Paths are used to load and store the required Data from and to the Memory Load and Store Instructions use an Address operator X: TU Dresden, 4/29/2008 chair Slide 34...
Addressing Modes There are two addressing modes supported: Linear Addressing Circular Addressing (e.g. Convolution) Circular Addressing supports block sizes 2 Only the lower N bits of the Address are modified by address arithmetic. This equals mod(2 The addressing mode is selected by control register „AMR‘...
Page 36
Floating vs. Fixed point processors Fixed point arithmetic 16-bit (integer or fractional) Signed or unsigned Floating point arithmetic 32-bit single precision 64-bit single precision Using signed and unsigned integers: Multiplication overflow. Addition overflow Saturate the result Double precision result Fractional arithmetic e.g.
Page 37
C6000 C Data Types Type Type char, signed char char, signed char unsigned char unsigned char short short unsigned short unsigned short int, signed int int, signed int unsigned int unsigned int long, signed long long, signed long unsigned long unsigned long enum enum...
Page 38
Numerical Issues - Useful Tips Multiply by 2: Divide by 2: Sine, Cosine, Log: To convert a fractional number to hex: Num x 2 Then convert to hex e.g: convert 0.5 to hex 0.5 x 2 (16384) TU Dresden, 4/29/2008 Use shift left Use shift right Use shift...
Page 39
Numerical Issues - 32-bit Multiplication It is possible to perform 32-bit multiplication using 16-bit multipliers. Example: c = a x b (with 32-bit values). a * b = (a = [(a TU Dresden, 4/29/2008 bits bits << 16 + a )* (b ) <<...
Page 42
The McBSP chair Multichannel Buffered Serial Port Up to 100 Mb/sec performance 2 (or 3) full-duplex, synchronous serial-ports Enables direct interfacing to industry standard Codecs, Analog interface Chips and other serially connected devices Supports a wide range of data-sizes, including 8, 12, 16, 20, 24 and 32 bits Bit, Word(channel), Frame, Phase In our lab the McBSP is used to connect to the A/D,...
Page 43
PCM3003 MONOLITHIC 20-BIT DS ADC AND DAC 16-/20-BIT INPUT/OUTPUT DATA HARDWARE CONTROL: PCM3003 STEREO ADC: STEREO DAC: Digital Attenuation (256 Steps), Soft Mute, Digital Loop Back SAMPLING RATE: Up to 48kHz SYSTEM CLOCK: 256f TU Dresden, 4/29/2008 SNR: 90dB & DynamicRange: 90dB SNR: 94dB &...
Page 44
What is the bootloader? EPROM EPROM C6211/C6711 C6211/C6711 When the DSP is NOT powered or under reset the internal program memory is in a random state. TU Dresden, 4/29/2008 Boot Config Boot Config Addr Addr 0000 0000 L1P Cache L1P Cache 0001 0001 0002...
Page 45
What is the bootloader? EPROM EPROM C6211/C6711 C6211/C6711 When the DSP is powered and the CPU is taken out of reset the internal memory is still in a random state and the program will start running for address zero. TU Dresden, 4/29/2008 Boot Config Boot...
Page 46
What is the bootloader? EPROM EPROM C6211/C6711 C6211/C6711 With the boot, a portion of code can be automatically copied from external to internal memory. TU Dresden, 4/29/2008 Boot Config Boot Config L1P Cache L1P Cache L1D Cache L1D Cache chair Slide 46...
Page 47
Interrupts chair DSPs must be able to execute tasks on asynchronous events Interrupts suspend the current processor task and save its context A interrupt service routine (ISR) is executed After completion of the ISR, the context of the former task is restored and the execution continues Interrupts are organized hierarchically vs.
Page 48
Interrupt Interrupt- and Thread Types TU Dresden, 4/29/2008 HWI priorities set by hardware One ISR per interrupt 14 SWI priority levels SWIs at each level 15 TSK priority levels TSKs at each level Multiple IDL functions Continuous loop HWI triggered by hardware interrupt IDL runs as the background thread chair Multiple...
Page 49
chair The DSK6711 Development Kit TU Dresden, 4/29/2008 Slide 49...
Page 50
DSK Contents Hardware 150 MHz ‘C6711 DSP TI 16-bit A/D Converter (‘AD535) External Memory 16M Bytes SDRAM 128K Bytes Flash ROM LED’s Daughter card expansion Power Supply & Parallel Port Cable Software Code Generation Tools (C Compiler, Assembler & Linker) Code Composer Debugger (256K program limitation) Example Programs &...
Page 51
C6711 DSK Overview 1.8V Power Supply 16M SDRAM Parallel Port I/F Power Jack Power 3.3V Power Supply JTAG Header TU Dresden, 4/29/2008 128K FLASH TMS320C6711 Reset 16-bit codec Emulation JTAG Header Line Level Input Line Level Output chair Daughter Card I/F (EMIF Connector) ‘C6711 D.
Page 52
Software: (4) PC TU Dresden, 4/29/2008 DSK Communications CCS uses parallel port to control DSP via JTAG port CCS uses parallel port to control DSP via JTAG port You can use full TI eXtended Dev System (XDS) via 14 pin You can use full TI eXtended Dev System (XDS) via 14 pin header connector header connector...
Page 53
What happens to the Source-Code? chair TU Dresden, 4/29/2008 Slide 53...