Yamaha Tyros3 Service Manual page 42

Tyros3
AK4396VF-E2 (X8324A00) DAC (Digital to Analog Converter)
PIN
NAME I/O
NO.
1 - Digital ground
DV
SS
2 - Digital power supply +3.3 V
DV
DD
3 MCLK I Master clock input
4 PDN I Power-down mode
5 BICK I Audio serial data clock
6 SDATA I Audio serial data input
7 I L/R clock
LRCK
8 I Soft mute/Chip select
SMUTE/CSN
9 I Sampling speed mode select/Chip address 0
DFS0/CAD0
10 I De-emphasis enable 0/Control data clock
DEM0/CCLK
11 I De-emphasis enable 1/Control data input
DEM1/CDTI
12 I
DIF0
Digital input format
13 DIF1 I
14 DIF2 I
DS99R103TSQX/NOPB (X9323A00) LVDS
PIN
NAME I/O
NO.
1 DIN[23:0] I
2 DIN[23:0] I Transmitter Parallel Interface Data Inputs Pins.
3 DIN[23:0] I Tie LOW if unused.
4 DIN[23:0] I
5 DCAOFF I RESERVED - This pin MUST be tied LOW.
6 VssL Digital Ground, Tx Logic Ground
7 V L Digital Voltage supply, Tx Logic Power
DD
8 DCBOFF I RESERVED - This pin MUST be tied LOW.
9 TPWDNB I Transmitter Power Down Bar
TPWDNB = H; Transmitter is Enabled and ON.
●
TPWDNB = L; Transmitter is in power down mode (Sleep),
●
LVDS Driver DOUT (+/-) Outputs are in TRI-STATE stand-by
mode, PLL is shutdown to minimize power consumption.
10 TCLK I Transmitter Parallel Interface Clock Input Pin.
Strobe edge set by TRFB configuration pin
11 TRFB I Transmitter Clock Edge Select Pin
TRFB = H; Parallel Interface Data is strobed on the Rising Clock Edge
●
TRFB = L; Parallel Interface Data is strobed on the Falling Clock Edge
●
12 VODSEL I VOD Level Select
VODSEL = L; LVDS Driver Output is ~400 mV (RL = 100 Ω)
●
VODSEL = H; LVDS Driver Output is ~800 mV (RL = 100 Ω)
●
For normal applications, set this pin LOW. For long cable ap-
plications where a larger VOD is required, set this pin HIGH.
13 RESRVD I RESERVED - This pin MUST be tied LOW.
14 V PT1 Analog Voltage supply, PLL Power
DD
15 VssPT1 Analog Ground, PLL Ground
16 V PT0 Analog Voltage supply, VCO Power
DD
17 VssPT0 Analog Ground, VCO Ground
18 DEN I Transmitter Data Enable
DEN = H; LVDS Driver Outputs are Enabled (ON).
●
DEN = L; LVDS Driver Outputs are Disabled (OFF),
●
Transmitter LVDS Driver DOUT (+/-) Outputs are in TRI-
STATE, PLL still operational and locked to TCLK.
42
FUNCTION
FUNCTION
PIN
NAME I/O
NO.
15 TTL I CMOS/TTL level select
16 VREFL I Low level voltage reference input
17 VREFH I High level voltage reference input
18 AV - Analog power supply +5 V
DD
19 AV - Analog ground
SS
20 AOUTR- O Rch negative analog output
21 AOUTR+ O Rch positive analog output
22 AOUTL- O Lch negative analog output
23 AOUTL+ O Lch positive analog output
24 VCOM O Common voltage output
25 P/S I Parallel/serial select
26 TST1/DZFL O Test 1/Lch zero input detect
27 TST2/CAD1 I Test 2/Chip address 1
28 ACKS/DZFR I/O Master clock auto setting mode/Rch zero input detect
PIN
NAME I/O
NO.
19 DOUT- O Transmitter LVDS Inverted (-) Output. This output is inten-
ded to be loaded with a 100 ohm load to the DOUT- pin.
20 DOUT+ O Transmitter LVDS True (+) Output. This output is intend-
ed to be loaded with a 100 ohm load to the DOUT+ pin.
21 VssDR O Analog Ground, LVDS Output Ground
22 V DR O Analog Voltage Supply, LVDS Output Power
DD
23 PRE I PRE-emphasis select pin.
PRE = (RPRE ≧ 3 kΩ); Imax = [(1.2/R) 20], Rmin = 3 kΩ
●
PRE = H or floating; pre-emphasis is disabled
●
24 Vss ESD Ground
25 DIN[23:0] I
26 DIN[23:0] I
Transmitter Parallel Interface Data Inputs Pins.
27 DIN[23:0] I
Tie LOW if unused.
28 DIN[23:0] I
29 DIN[23:0] I
30 V T Digital Voltage supply, Tx Serializer Power
DD
31 VssT Digital Ground, Tx Serializer Ground
32 DIN[23:0] I
33 DIN[23:0] I
34 DIN[23:0] I
35 DIN[23:0] I
36 DIN[23:0] I Transmitter Parallel Interface Data Inputs Pins.
37 DIN[23:0] I Tie LOW if unused.
38 DIN[23:0] I
39 DIN[23:0] I
40 DIN[23:0] I
41 DIN[23:0] I
42 V IT I Digital Voltage supply, Tx Input Power
DD
43 VssIT I Digital Ground, Tx Input Ground
44 DIN[23:0] I
45 DIN[23:0] I
Transmitter Parallel Interface Data Inputs Pins.
46 DIN[23:0] I
Tie LOW if unused.
47 DIN[23:0] I
48 DIN[23:0] I
DM: IC900, 901
FUNCTION
DM: IC8
FUNCTION