Yamaha Tyros3 Service Manual page 39

S1L52502F24J200 (X2688A0R) GATE ARRAY
PIN
NAME I/O
NO.
1 LV Power supply +3.3V
DD
2 XDACK I CPU DMA acknowledge
3 XDRAK I CPU DREQ request acknowledge
4 XDREQ O CPU DMA request
5 ATPGEN I ATPG test input
6 Vss Ground
7 ENCA0 I Encoder0 A input
8 ENCB0 I Encoder0 B input
9 ENCA1 I Encoder1 A input
10 ENCB1 I Encoder1 B input
11 HV Power supply +5V
DD
12 ENCA2 I Encoder2 A input
13 ENCB2 I Encoder2 B input
14 ENCA3 I Encoder3 A input
15 ENCB3 I Encoder3 B input
16 Vss Ground
17 ENCA4 I Encoder4 A input
18 ENCB4 I Encoder4 B input
19 ENCA5 I Encoder5 A input
20 ENCB5 I Encoder5 B input
21 HV Power supply +5V
DD
22 TSTEN I Test mode change
23 XIDCS0 O
IDE chip select
24 XIDCS1 O
25 XIDDOE O IDE bus buffer DIR signal
26 Vss Ground
27 HV Power supply +5V
DD
28 XIDWR O IDE write signal
29 XIDRD O IDE read signal
30 XIDMACK O IDE DMA acknowledge
31 IDMARQ I IDE DMA request
32 Vss Ground
33 IDD0 I/O
34 IDD1 I/O
IDE data bus
35 IDD2 I/O
36 IDD3 I/O
37 HV Power supply +5V
DD
38 IDD4 I/O
39 IDD5 I/O
IDE data bus
40 IDD6 I/O
41 IDD7 I/O
42 Vss Ground
43 IDD8 I/O
44 IDD9 I/O
IDE data bus
45 IDD10 I/O
46 IDD11 I/O
47 HV Power supply +5V
DD
48 IDD12 I/O
49 IDD13 I/O
IDE data bus
50 IDD14 I/O
51 IDD15 I/O
52 Vss Ground
53 LV Power supply +3.3V
DD
54 SDRD0 I/O
55 SDRD1 I/O
SDRAM data bus
56 SDRD2 I/O
57 SDRD3 I/O
58 Vss Ground
59 SDRD4 I/O
60 SDRD5 I/O
SDRAM data bus
61 SDRD6 I/O
62 SDRD7 I/O
63 LV Power supply +3.3V
DD
64 SDRD8 I/O
65 SDRD9 I/O
SDRAM data bus
66 SDRD10 I/O
67 SDRD11 I/O
68 Vss Ground
69 SDRD12 I/O
70 SDRD13 I/O
SDRAM data bus
71 SDRD14 I/O
72 SDRD15 I/O
73 LV Power supply +3.3V
DD
74 SDRA0 O
75 SDRA1 O
SDRAM address output
76 SDRA2 O
77 SDRA3 O
78 Vss Ground
79 LV Power supply +3.3V
DD
80 SDRA4 O
81 SDRA5 O
SDRAM address output
82 SDRA6 O
83 SDRA7 O
84 Vss Ground
85 SDRA8 O
86 SDRA9 O
SDRAM address output
87 SDRA10 O
88 SDRA11 O
89 LV Power supply +3.3V
DD
90 SDRA12 O
SDRAM address output
91 SDRA13 O
92 XSDRWE O SDRAM write signal
93 XSDRRAS O SDRAM row address strobe
94 Vss Ground
95 XSDRCAS O SDRAM column address strobe
96 XSDRCS0 O
SDRAM chip select
97 XSDRCS1 O
98 SDRDQM O SDRAM data enable
99 LV Power supply +3.3V
DD
100 SDRCLK O SDRAM clock
101 XTCLR I Test counter clear
102 HV Power supply +5V
DD
103 TESTRAM I RAM test mode
104 Vss Ground
PIN
FUNCTION
NO.
105
106
107
108
109
110
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
NAME I/O
HV Power supply +5V
DD
LEDD0
O
LEDD1
O
Port/Test output
LEDD2
O
LEDD3
O
Vss Ground
111 LV Power supply +3.3V
DD
XTA22I XTAL input terminal
I
Vss Ground
XTA22O O XTAL output terminal
LV Power supply +3.3V
DD
HV Power supply +5V
DD
LEDD4 O
LEDD5 O
Port/Test output
LEDD6 O
LEDD7 O
Vss Ground
VCOI I VCO clock input
HV Power supply +5V
DD
PDOUT PLL phase comparator output
O
Vss Ground
XRESET Reset signal input
I
EXTWCI External synchronization WC input
I
SDIN Digital sound input
I
SDOUT Digital sound output
O
HV Power supply +5V
DD
XDSPCS0 DSP6 chip select
O
XDSPCS2 DSP chip select (reserve)
O
XDSPCS1 DSP7 chip select
O
Vss Ground
AUDIOIN0 I
Audio data input
AUDIOIN1 I
AUDIOUT0 O Audio data output
LV Power supply +3.3V
DD
AUDIOUT1 O
AUDIOUT2 O Audio data output
AUDIOUT3 O
Vss Ground
AUDIOUT4 O
AUDIOUT5 Audio data output
O
AUDIOUT6
O
LV Power supply +3.3V
DD
HV Power supply +5V
DD
CK512 FS512 clock
O
FS256 FS256 clock
O
FS128 FS128 clock
O
Vss Ground
XFS64 FS64 clock (reverse)
O
ALRCK System WC (FS)
O
XSSYNC O DSP synchronizing signal output
HV Power supply +5V
DD
Vss Ground
LV Power supply +3.3V
DD
HV Power supply +5V
DD
XDLCS O Data buffer enable
XLCDCS0 O
LCD driver chip select
XLCDCS1 O
Vss Ground
CD0 I/O
CD1
I/O
CPU data bus
CD2
I/O
CD3
I/O
LV Power supply +3.3V
DD
CD4
I/O
CD5
I/O
CPU data bus
CD6
I/O
CD7
I/O
Vss Ground
CD8
I/O
CD9 I/O
CPU data bus
CD10 I/O
CD11 I/O
LV Power supply +3.3V
DD
CD12 I/O
CD13 I/O
CPU data bus
CD14 I/O
CD15 I/O
Vss Ground
LV Power supply +3.3V
DD
CA1
I
CA2
I
CPU address input
CA3
I
CA4
I
Vss Ground
CA5
I
CA6
I
CPU address input
CA7
I
CA12
I
LV Power supply +3.3V
DD
CA13 I
CPU address input
CA16 I
XCCS5 I
CPU chip select
XCCS6 I
Vss Ground
XCRD I CPU read signal
XCWR I CPU write signal
XCIRQ O
CPU interrupt request
XFTMIRQ1 O
LV Power supply +3.3V
DD
XFTMIRQ2
O
CPU interrupt request
XFTMIRQ3
O
FSPLAY FS count signal
O
SCANEN Scan enable input
I
Vss Ground
Tyros3
DM: IC203
FUNCTION
39