Sony CDU31A Series Service Manual page 51

CXD2500BO 12/21
Pin Oescripption
Pin
Pin
1/0
Description
No.
Sign
Pin Pin
1/0 Description
No. Sion
1
FOK I
Focus OK input terminal
2
FSW 0
z.
0 SPindle motor output filter select outout
43 DA07
0
1. 0
On PSSL • 1. DA07 output.
On
PSSL • 0. RFCK output
3
MON 0
1. 0 Spindle motor ON-OFF control output
4 MOP
·o
1,
z.
0 Soindle motor servo control
" DA06 0 1, 0
On
PSSL • 1, DA06 output.
On PSSL • 0. C2PO output.
5
MOS 0 1,
z.
0
Spindle motor servo control
6 LOCK
0 1, 0
When GFS is High, High output. When GFS is low
8
times continuoualv. Low output.
7
NC
45 DAOS
0 1, 0
On PSSL • 1. DA05 output.
On
PSSL • 0. XRAOF output.
46
DA04 0 1. 0
On
PSSL • I, DA04 output.
On
PSSL • 0. MNT3 output.
8
vcoo
0
1. 0 Analogue EFM PLL oscillating circuit output.
9 VCOI I
Analogue EFM PLL oscillating circuit input.
fLoar: • 8.6436MHz
10
TEST I Terminel for TEST. On:tin•rily connected to GND.
47 DA03
0
1. 0
On
PSSL • 1, OA03 output.
On PSSL • 0. MNT2 output.
48
DA02 0
1, 0
On PSSL • I, DA02 output.
On PSSL • 0. MNTl output.
11
PDO 0
1,
z.
0
Anologue EFM PLL cho1119 pump output
12 Va GND
49 DA01 0 1, 0
On PSSL • 1, DAOl output.
On PSSL • O. MNTO output.
13
NC 50 APTR
0
I, 0 Aperture correction control outPUt.
On
Reh, H.
14
NC 51 APTL
0
1, 0 Aperture COF1'9Ction control output. On Leh. H.
15
NC
52 Vu
GNO
16
VPCO 0
1,
z.
0
Vary oitch PLL charge pump output
17 VCKI I
Clock in..Ut f-... • 1 B.9344MHz from externel VCO
for vary pitch.
53
XTAI I
16.93-UMHz crvstel oscillating circuit input.
Or
33.8688MHz input.
54 XTAO 0 1, 0 16.934'MHz Crytltll 01cill1ting circuit OUtPUt
18 FILO 0 anelooue Filter output for master PLL (slave • digital
PLL)
Crvst11 nlect input termin1I. When crvstel is
19 FILI I Filter input for master PLL
55
XTSL I 16.9334MHz. it bocomoo
L.
when 33.8688MHz,
20 PCO 0
1,
z.
0
Charge
pump output for mHter
PLL
becom11 H.
21 AV11
Anologue GND
22 CLTV I VCO control voltage input for master
56
FSTT 0
1, 0
2/3 dividing output of Pina 53 end 54.
Not changing by verv pitch.
23
AVoo
Anolo;ue - supply (
+
5V)
24 RF I EFM •i;nal input
57 CIM
0 1.
0
4.2336MHz output.
When
pitch is varied,
it
chenoea et the urne time.
25 BIAS I Auymmetrv
circuit
constant curTW'lt input
26 ASYl I
Auvmmetrv comoerete
volt.oe
input
58 CIBM 0 1, 0
1B.9344MHz output. When pitch is veriod.
It
chenon at
the
urne
tirna.
27 ASYO 0 1, 0 EFM full-owing outDut (L • Vu, H • Voo) 59 MD2 I Oigitol-Out ON/OFF control. H : ON. L : OFF
28 ASYE I
L : Aaavmmetry circuit OFF
H : A1symmetry circuit
Of\I
29
NC
60 DOUT 0 1, 0 Digit11-0ut output terminel
61 EMPH
0
1. 0
Whlin tM playback disc ii empheaincf, H i1 out.
not aml>h81inct, L is out.
30 PSSL I
Audio data output
mode Mlect
input
L : Soriol output/H : 1'8rallel output
31 WDCK
0
D/ A interfeco for 48 bit slot
62 WFCK 0 1, 0 WFCK (Write Fram• Clock) oulPUt
63 SCOR 0 1, 0
When
the
1ubcodo sync. SO or Sl is dotoctod,
H is out.
32 LACK 0 D/ A interfeco for 48 bit •lot 64 $8SO 0 1. 0 SubP to W nriol output
33 Voo
Power
oupply (
+
5Vl
65
EXCK
I S8SO rud-out clock input
34 DA16 0· 1, 0
On
PSSL • 1, DA 16 (MSB) output.
On PSSL • 0. 48 bit slot Hri•I dot•.
66 SOSO 0 I. 0 SubO 80bit •nd PCM - k level doto 16bit output
67 SOCK I SOSO raockut clock Input
35 OA15
0 1, 0
On
PSSL • 1, DA 15 output.
On PSSL • 0. 48 bit slot bit clock.
68
MUTE I H : Muto
on.
L : Muto off
89
SENS
-
1,
z.
0 SENS output to CPU
36 DA14
0
1, 0
On
PSSL • 1, DA 14 output.
On PSSL •
O.
64 bit slot Hriel doto.
70 XRST I
System reset. Au.t on "L"
71 DATA I S.riol doto input from CPU
37 DA13
0 1, D
On
PSSL • 1, DA 13 output.
On
PSSL • O. 64 bit slot bit clock.
72 XLAT I
Lach input from CPU. Utch uri1l deta on felling
odgo
36 DAl2 0 1, 0
On PSSL • 1, DA 12 output.
On PSSL • 0. 64 bit slot LR clock.
73 Voo
- · ouPPlv (
+
5V)
74 CLOK I Serial data transfer clock input from CPU
39 DAil 0 I, 0
On PSSL • 1, DA 11 output.
On PSSL • 0. GTOP output.
75 SEIN
I Sense
input from SSP
76 CNIN
I
Track jump numbers count lional input
40 DA10 0 1, 0
On PSSL • 1, DA10 output.
On PSSL •
0.
XUGF ouput.
•1
DA09 0 1, 0
On PSSL • 1, DA09 output.
On PSSL • 0. XPLCK output.
n.
DATO
0 I, 0
Serial dete outPUt to SSP
78
XLTO
0
1. 0
Serial date latch output to SSP. t..tch on felling
•..
79 CLKO
0
1, 0
Serial date trenafer clock output to SSP
42 DAOB 0 1, 0
On PSSL • 1. DA08 output.
On PSSL • O. GFS output.
80 MIRR I Miror stanal inPUt
7-8.