Advertisement
T
S
8
G
S
S
D
2
5
-
S
T
S
8
G
S
S
D
2
5
-
S
T
S
8
G
S
S
D
2
5
-
S
T
S
1
6
G
S
S
D
2
5
-
S
T
S
1
6
G
S
S
D
2
5
-
S
T
S
1
6
G
S
S
D
2
5
-
S
T
S
3
2
G
S
S
D
2
5
-
S
T
S
3
2
G
S
S
D
2
5
-
S
T
S
3
2
G
S
S
D
2
5
-
S
T
S
6
4
G
S
S
D
2
5
-
S
T
S
6
4
G
S
S
D
2
5
-
S
T
S
6
4
G
S
S
D
2
5
-
S
T
S
1
2
8
G
S
S
D
2
5
-
T
S
1
2
8
G
S
S
D
2
5
-
T
S
1
2
8
G
S
S
D
2
5
Name
Comment
t
Typical sustained average two cycle time
2CYCTYP
t
Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge)
CYC
t
Two cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to
2CYC
next falling edge of STROBE)
t
Data setup time at recipient (from data valid until STROBE edge)
DS
t
Data hold time at recipient (from STROBE edge until data may become invalid)
DH
t
Data valid setup time at sender (from data valid until STROBE edge)
DVS
t
Data valid hold time at sender (from STROBE edge until data may become invalid)
DVH
t
CRC word setup time at device
CS
t
CRC word hold time device
CH
t
CRC word valid setup time at host (from CRC valid until DMACK- negation)
CVS
t
CRC word valid hold time at sender (from DMACK- negation until CRC may become invalid)
CVH
t
Time from STROBE output released-to-driving until the first transition of critical timing.
ZFS
t
Time from data output released-to-driving until the first transition of critical timing.
DZFS
t
First STROBE time (for device to first negate DSTROBE from STOP during a data in burst)
FS
t
Limited interlock time
LI
t
Interlock time with minimum
MLI
t
Unlimited interlock time
UI
t
Maximum time allowed for output drivers to release (from asserted or negated)
AZ
t
Minimum delay time required for output
ZAH
t
drivers to assert or negate (from released)
ZAD
t
Envelope time (from DMACK- to STOP and HDMARDY- during data in burst initiation and from DMACK
ENV
to STOP during data out burst initiation)
t
Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of DMARDY-)
RFS
t
Ready-to-pause time (that recipient shall wait to pause after negating DMARDY-)
RP
t
Maximum time before releasing IORDY
IORDYZ
t
Minimum time before driving IORDY
ZIORDY
t
Setup and hold times for DMACK- (before assertion or negation)
ACK
t
Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates a burst)
SS
Transcend Information Inc.
/
M
/
M
/
M
/
M
/
M
/
M
M
M
-
M
31
2.5" Solid State Disk
V1.08
Advertisement
