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Rockwell RCVDL56DPFL/SP Designer's Manual

Modem data pump
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RCVDL56DPFL/SP,
RCV56DPFL/SP, and
RCV336DPFL/SP Modem Data Pump
Designer's Guide
(Preliminary)
Order No. 1119
February 27, 1997

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Summary of Contents for Rockwell RCVDL56DPFL/SP

  • Page 1 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Modem Data Pump Designer's Guide (Preliminary) Order No. 1119 February 27, 1997...
  • Page 2 Information furnished by Rockwell International Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Rockwell International for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Rockwell International other than for circuitry embodied in Rockwell products.

  • Page 3: Table Of Contents

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table of Contents 1. INTRODUCTION .............................1-1 1.1 SUMMARY............................1-1 1.2 FEATURES ............................1-2 1.3 TECHNICAL DESCRIPTION........................1-3 1.3.2 AudioSpan Modes .......................1-5 1.3.3 Data Formats ........................1-6 2. HARDWARE INTERFACE..........................2-1 2.1 HARDWARE INTERFACE SIGNALS ....................2-1 2.2 LINE TRANSFORMER REQUIREMENTS FOR V.34/V.32 ..............2-16 3.
  • Page 4 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 6.8 CLEARDOWN ...........................6-10 6.8.1 K56flex Cleardown ......................6-10 6.8.2 V.34 Cleardown......................... 6-10 6.8.3 V.32 bis Cleardown ......................6-10 7. DESIGN CONSIDERATIONS ..........................7-1 7.1 PC BOARD LAYOUT GUIDELINES .....................7-1 7.2 ELECTROMAGNETIC INTERFERENCE (EMI) CONSIDERATIONS ............7-3 7.3 CRYSTAL SPECIFICATIONS ......................7-5...
  • Page 5 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 12. SIMULTANEOUS AUDIO/VOICE AND DATA (AUDIOSPAN) ..............12-1 12.1 ML144/V.61 (V.32bis) AUDIOSPAN CONTROL ................12-1 12.1.1 AudioSpan Control Registers................... 12-1 12.1.2 ML144 Mode Selection....................12-2 12.1.3 Detecting Remote Off-Hook Status.................. 12-2 12.1.4 Generating Ring and Ringback ..................12-2 12.1.5 ML144/V.61 AudioSpan Rate Sequence ................
  • Page 6 Figure 2-1. RCV336DPFL/SP Modem Functional Interface Signals ..................2-2 Figure 2-2. RCV56DPFL/SP Modem Functional Interface Signals ..................2-2 Figure 2-3. RCVDL56DPFL/SP Modem Functional Interface Signals..................2-3 Figure 2-4. MDP Pin Signals - 144-Pin TQFP........................2-4 Figure 2-5. Host Bus Interface Waveforms ........................2-14 Figure 2-6.
  • Page 7 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Figure 8-13. Answering a Fax Call - Phase D........................8-15 Figure 8-14. Transmitting FSK/HDLC Signals........................8-16 Figure 8-15. Low Speed Configuration Routine ........................ 8-17 Figure 8-16. Transmit Preamble Routine.......................... 8-18 Figure 8-17. Transmit Parallel Data Routine........................8-19 Figure 8-18.
  • Page 8 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide List of Tables Table 1-1. Modem Models and Differences ........................1-1 Table 1-2. Configurations, Signaling Rates, and Data Rates....................1-4 Table 1-3. RTS-CTS Response Times ..........................1-5 Table 2-1. MDP Pin Signals - 144-Pin TQFP........................2-5 Table 2-2. MDP Signal Definitions............................2-7 Table 2-3.
  • Page 9 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 14-1. K56flex Data Rate Versus Configuration and Data Rate Mask Values............14-2 Table 14-2. K56flex Data Rate Versus Speed Bit Values....................14-2 Table 14-3. ARA Values ..............................14-6 Table 14-4. Speed Selection............................14-6 1119...
  • Page 10 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide This page is intentionally blank. 1119...

  • Page 11: Introduction

    1. INTRODUCTION 1.1 SUMMARY The Rockwell RCV336DPFL/SP is a V.34 modem data pump (MDP) family that supports data rates up to 33600 bps, fax operation up to 14400 bps, AudioSpan (simultaneous audio/voice and data), voice coding/decoding (optional), and speakerphone (optional).

  • Page 12: Features

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 1.2 FEATURES • Downloadable MDP code from the host (RCDL56 only) • 2-wire full-duplex − K56flex (RC56 and RCDL56 only) − 33.6 kbps, 31.2 kbps, V.34, V.32 bis, V.32, V.22 bis, V.22, V.23, and V.21 −...

  • Page 13: Technical Description

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 1.3 TECHNICAL DESCRIPTION Configurations and Rates The selectable MDP configurations, signaling rates, and data rates are listed in Table 1-2. Automatic Mode Selection When automatic mode selection (AMS) is enabled, the MDP configures itself to the highest compatible data rate supported by the remote modem (AUTO bit).

  • Page 14: Table 1-2. Configurations, Signaling Rates, And Data Rates

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 1-2. Configurations, Signaling Rates, and Data Rates Carrier Frequency Data Rate (bps) Symbol Rate Bits/Symbol Bits/Symbol - Constellation Configuration Modulation (Hz) ±0.01% ±0.01% (Symbols/Sec.) - Data Points K56flex PCM 4 – 56000R/V.34T 8000 Dynamic –...

  • Page 15: Audiospan Modes

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 1-3. RTS-CTS Response Times RTS-CTS Response Configuration Constant Carrier Controlled Carrier Turn-Off Sequence K56flex (RC56DPFL), ± 2 ms V.34, V.32 bis, V.32 V.33/V.17 Long 1393 ms 15 ms V.33/V.17 Short 142 ms 15 ms V.29...

  • Page 16: Data Formats

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Speakerphone Voice/Audio Paths (Optional) The MDP incorporates a dual integrated analog interface. The voice/audio transmit and receive signals can be routed through several paths. The voice/audio paths are available in the speakerphone mode configuration and are selected through DSP RAM.
  • Page 17 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Async/Sync and Sync/Async Conversion An asynchronous-to-synchronous converter is provided in the transmitter and a synchronous-to-asynchronous converter is provided in the receiver. The converters operate in both serial and parallel modes. The asynchronous character format is 1 start bit, 5 to 8 data bits, an optional parity bit, and 1 or 2 stop bits.
  • Page 18 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 511 Pattern Generation/Detection In a synchronous mode, a 511 pattern can be generated and detected (control bit S511). Use of this bit pattern during self- test eliminates the need for external test equipment. In-Band Secondary Channel A full-duplex in-band secondary channel is provided in V.34 (all speeds) and V.32 bis/V.32 (7200 bps and above) modes.

  • Page 19: Hardware Interface

    The functional interconnect diagram in Figure 2-1 (RCV336DPFL/SP), Figure 2-2 (RCV56DPFL/SP), and Figure 2-3 (RCVDL56DPFL/SP) show the typical MDP connections in a system. In these diagrams, any point that is active low is represented by a small circle at the signal point.

  • Page 20: Figure 2-1. Rcv336Dpfl/Sp Modem Functional Interface Signals

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide ~RDCLK XTLI TDCLK CRYSTAL XTLO XTCLK ~RLYA V.24 SERIAL ~RTS ~RLYB ~CTS RINGD INTERFACE TELEPHONE ~DTR LINE RC336DPFL ~DSR TXA1 RCV336DPFL TELEPHONE LINE/ ~RLSD TXA2 TELIN TELEPHONE/ RCV336DPFL/SP TELEPHONE TELIN AUDIO INTERFACE TELOUT LINE...

  • Page 21: Figure 2-3. Rcvdl56Dpfl/Sp Modem Functional Interface Signals

    DATA PUMP INTERFACE TELOUT (R6775:144-PIN TQFP) MICV ~READ MICM MIC/ SPKR ~WRITE SPEAKER DATA BUS (8) D0-D7 SPKMD ADDRESS BUS (5) A0-A4 RS0-RS4 HOST PROCESSOR DECODER POWER AGND SUPPLY ~RESET DGND MD183F1 FID Figure 2-3. RCVDL56DPFL/SP Modem Functional Interface Signals 1119...

  • Page 22: Figure 2-4. Mdp Pin Signals - 144-Pin Tqfp

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide MD180F5 PO-MDP144T Figure 2-4. MDP Pin Signals - 144-Pin TQFP 1119...

  • Page 23: Table 2-1. Mdp Pin Signals - 144-Pin Tqfp

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 2-1. MDP Pin Signals - 144-Pin TQFP Interface 3 Signal Label I/O Type Signal Label I/O Type Interface IA/OB Host Parallel Interface SR2CLK To VSCLK (55) VDD through 10K Ω RESERVED TIRO2 IA/OB...
  • Page 24 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 2-1. MDP Pin Signals - 144-Pin TQFP (Continued) Signal Label I/O Type Interface3 Signal Label I/O Type Interface To PLLVDD through 0.1 µ F PLLGND DGND (Note 4) RESERVED GPO0 To ~RDCLK (71)

  • Page 25: Table 2-2. Mdp Signal Definitions

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 2-2. MDP Signal Definitions Label I/O Type Signal/Definition OVERHEAD SIGNALS Crystal In and Crystal Out. Connect the MDP to an external crystal circuit consisting of a 56.448 MHz crystal, XTLI, XTLO I, O three capacitors, and an inductor.
  • Page 26 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 2-2. MDP Signal Definitions (Cont'd) Label I/O Type Signal Name/Description PARALLEL HOST INTERFACE Address, data, control, and interrupt hardware interface signals allow MDP connection to an 8086-compatible microprocessor bus. With the addition of external logic, the interface can be made compatible with a wide variety of other microprocessors such as the 6502, 8086 or 68000.
  • Page 27 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 2-2. MDP Signal Definitions (Cont'd) Label I/O Type Signal Name/Description DTE SERIAL INTERFACE Timing, data, control, and status signals provide a V.24-compatible serial interface. These signals are TTL compatible in order to drive the short wire lengths and circuits normally found within a printed circuit board, stand-alone modem enclosures, or equipment cabinets.
  • Page 28 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 2-2. MDP Signal Definitions (Cont'd) Label I/O Type Signal Name/Description TELEPHONE LINE/TELEPHONE/AUDIO INTERFACE SIGNALS AND REFERENCE VOLTAGE TXA1, TXA2 O(DF) Transmit Analog 1 and 2 Output. The TXA1 and TXA2 outputs are differential outputs 180 degrees out of phase with each other.
  • Page 29 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 2-2. MDP Signal Definitions (Cont'd) Label I/O Type Signal Name/Description MISCELLANEOUS ~WKRES Wake-up Reset. Active low reset signal used to wake up connected peripheral devices from Sleep Mode (RCDL56 only) or reserved function with no external connection allowed (RC336 and RC56).

  • Page 30: Table 2-3. Digital Electrical Characteristics

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 2-3. Digital Electrical Characteristics Parameter Symbol Min. Typ. Max. Units Test Conditions 1 Input High Voltage Type IA and IB – Type ID 0.8 V – Input High Current – – µA Input Low Voltage Input Low Current –...

  • Page 31: Table 2-5. Current And Power Requirements

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 2-5. Current and Power Requirements Typical Maximum Typical Maximum Notes Mode Current Current Power Power (mA) (mA) (mW) (mW) Normal mode f IN = 56.448 MHz Sleep mode — — Notes: 1. Test conditions: VCC = 5.0 VDC for typical values; VCC = 5.25 VDC for maximum values.

  • Page 32: Figure 2-5. Host Bus Interface Waveforms

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide RS0-RS4 ~READ TDHR D0-D7 a. Host Bus Read RS0-RS4 ~WRITE TWDS D0-D7 TWDH b. Host Bus Write * A minimum delay of 3 times the YCLK cycle time is required from the rising edge of ~WRITE to the falling edge of the next selected ~READ or ~WRITE.

  • Page 33: Figure 2-6. Dte Serial Interface Waveforms

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide TDCLK 4800 BPS 4800 BPS TDCLK 9600 BPS 9600 BPS NOTE: THIS FIGURE IS VALID FOR SYNCHRONOUS MODE ONLY. THERE IS NO RELATIONSHIP BETWEEN NOTE: TXD AND TDCLK IN ASYNCHRONOUS MODE. a. Transmit RDCLK...

  • Page 34: Line Transformer Requirements For V.34/V.32

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 2.2 LINE TRANSFORMER REQUIREMENTS FOR V.34/V.32 K56flex/V.34/V.32 bis/V.32 places high requirements upon the Data Access Arrangement (DAA) to the telephone line. Any non-linear distortion generated by the DAA in the transmit direction cannot be canceled by the MDP's echo canceller and interferes with data reception.

  • Page 35: Software Interface

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 3. SOFTWARE INTERFACE Modem data pump functions are implemented in MDP DSP firmware (code). 3.1 INTERFACE MEMORY The MDP DSP communicates with the host processor by means of a dual-port, interface memory. The interface memory contains thirty-two 8-bit registers, labeled register 00 through 1F.

  • Page 36: Figure 3-1. Modem Interface Memory Map

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Register (Hex) NSIA NCIA — NSIE NEWS NCIE — NEWC TDBIA RDBIA TDBIE — TDBE RDBIE — RDBF MEACC — MEMW MEMCR Memory Access Address High B11-B8 (MEADDH) Memory Access Address Low B7-B0 (MEADDL)

  • Page 37: Table 3-1. Interface Memory Bit Definitions

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions Mnemonic Location Default Name/Description AA Detector. When set, status bit AADET indicates that a V.32 bis/V.32 AA sequence AADET 0Ch:7 – has been detected. This bit is reset by the MDP at the start of the CC sequence. This bit is not valid during rate renegotiation.
  • Page 38 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont’d) Mnemonic Location Default Name/Description Automatic Mode Change Enable. When control bit AUTO is set, the MDP will AUTO 15h:3 automatically determine the communication standard of the remote modem and configure itself accordingly.
  • Page 39 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description CONF 12h:7-0 Modem Configuration. The CONF control bits select the MDP configuration from the following codes: Mode Data Rate CONF (Hex) K56flex 32000-56000...
  • Page 40 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont’d) Mnemonic Location Default Name/Description CONF 12h:0–7 Modem Configuration (Cont’d). NOTES: The MDP can transmit a GSTN Cleardown sequence during a retrain (V.32 bis/V.32) or a rate renegotiation (K56flex, V.34/V.32 bis/V.32).
  • Page 41 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont’d) Mnemonic Location Default Name/Description DISDET 0Bh:1 – Disconnect Detect. When set, status bit DISDET indicates that a line disconnection has occurred and the MDP has synchronized onto it's own transmit signal (i.e., EQM acceptable and RLSD still on).
  • Page 42 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont’d) Mnemonic Location Default Name/Description 09h:0 Data Terminal Ready. In K56flex, V.8, V.34, V.32 bis/V.32, V.22/V.22 bis, and Bell 212A modes, setting control bit DTR initiates a handshake sequence, providing DATA bit is set.
  • Page 43 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont’d) Mnemonic Location Default Name/Description Framing Error. When set, status bit FE indicates that more than 1 in 8 (or 1 in 4 for 0Ah:4 extended overspeed) characters were received without a Stop bit in asynchronous mode or an ABORT sequence was detected in SDLC/HDLC synchronous mode.
  • Page 44 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont’d) Mnemonic Location Default Name/Description Loop 2 Activate. When control bit L2ACT is set, the receiver's digital output is L2ACT 07h:5 connected to the transmitter's digital input (locally activated remote digital loopback) in accordance with V.54.
  • Page 45 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description MEMCR 1Dh:4 Memory Continuous Read. When set to a 1, control bit MEMCR instructs the DSP to automatically update the data in MEDAM and MEDAL based on the RAM address in MEADDH and MEADDL.
  • Page 46 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description NSIE 1Fh:4 NEWS Interrupt Enable. When control bit NSIE is set (interrupt enabled), the MDP will assert IRQ and set NSIA when NEWS is set by the MDP. When NSIE is reset (interrupt disabled), NEWS has no effect on IRQ or NSIA.
  • Page 47 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont’d) Mnemonic Location Default Name/Description Receive Data Buffer. The host obtains channel data from the MDP receiver in the RBUFFER 00h:7-0 – parallel data mode by reading a data byte from the RBUFFER. The RBUFFER contains the received data when the RDBF bit is set.
  • Page 48 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont’d) Mnemonic Location Default Name/Description Rate Renegotiation. If control bit RREN is set in K56flex, V.34 or V.32 bis data mode, RREN 15h:2 a rate negotiation sequence is initiated. RREN resets as soon as the initiation is acknowledged.
  • Page 49 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont’d) Mnemonic Location Default Name/Description Rate Sequence Received. When status bit RSEQ is set, the 16-bit rate sequence RSEQ 0Ch:0 included in the start-up procedure has been received and is available in RAM. RSEQ will remain set until reset by the host.
  • Page 50 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description 08h:0 Request to Send. When control bit RTS is set, the MDP transmits any data on TXD (TPDM = 0) or TBUFFER (TPDM = 1) when CTS becomes active.
  • Page 51 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description S1DET 0Dh:5 – S1 Detector. When set, status bit S1DET indicates that a V.22 bis S1 sequence has been detected. This bit is reset by the MDP at the end of the S1 sequence. (V.22 bis)
  • Page 52 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont’d) Mnemonic Location Default Name/Description Sleep Mode. When control bit SLEEP is set, the MDP is placed in sleep mode for SLEEP 15h:7 reduced power consumption and the SLEEP pin is driven low. The MDP can be awakened only if bit RDWK and/or HWRWK is set.
  • Page 53 V.34 which causes no interruption of primary data. This is a proprietary method and will only work if both MDPs are Rockwell data pumps. This compatibility is enforced by communicating the seamless rate change capability during the handshake. The rate change request is communicated over the MDP's secondary channel.
  • Page 54 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description TBUFFER 10h:7-0 Transmit Data Buffer. The host conveys output data to the transmitter in the parallel mode by writing a data byte to the TBUFFER. Parallel data mode is available in both synchronous and asynchronous modes.
  • Page 55 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description 0Fh:2 – Test Mode. When set, status bit TM indicates that the MDP is in RDL test mode. The TM bit will be set when RLSD turns off at the start of RDL, and will reset less than 100 ms prior to RLSD turning back on at the end of RDL.
  • Page 56 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description TXSQ 05h:4 Transmitter Squelch. When control bit TXSQ is set, the transmitter analog output is squelched. All other transmitter functions continue as normal. When TXSQ is reset, the transmitter output functions normally.
  • Page 57 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont'd) Mnemonic Location Default Name/Description V54DT 0Fh:0 V.54 Pattern Detected. When set, status bit V54DT indicates that one of the three V.54 patterns is being detected. Only one of the three detector enabling bits (V54PE, V54AE or V54TE) must be set by the host at any given time.
  • Page 58 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-1. Interface Memory Bit Definitions (Cont’d) Mnemonic Location Default Name/Description Voice Pause. Control bit VPAUSE enables (1) or disables (0) the voice “pause.” When VPAUSE 01h:5 VPAUSE is enabled, voice data is not output to the host.

  • Page 59: Table 3-2. Abcode Error Code Definitions

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-2. ABCODE Error Code Definitions Value (Hex) Description Mode FED turned off while waiting to get into round trip delay estimate (RTDE) V.32 Unexpected E-sequence, do retrain V.32 Timed out in rate renegotiation V.34...
  • Page 60 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 3-2. ABCODE Error Code Definitions (Cont’d) Value (Hex) Description Mode Problem with S-sequence in phase 4 V.34 FED turned off during S-sequence in phase 4 V.34 S-sequence turned off before expected in phase 4 V.34...

  • Page 61: Dsp Ram Access

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 4. DSP RAM ACCESS The MDP DSP contains a 16-bit wide random access memory (RAM). The host processor can access (read or write) the RAM through a 12-bit memory address in registers 1D and 1C.

  • Page 62: Table 4-1. Interface Memory Ram Addresses

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 4-1. Interface Memory RAM Addresses Function Method Address (Hex) V.34 Transmitter and K56flex/V.34 Receiver Speeds V.34 Transmitter Speed K56flex/V.34 Receiver Speed Rate Sequence Received R Received E Transmitted R 2 (RO) 205, 204 (see Note 1)
  • Page 63 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 4-1. Interface Memory RAM Addresses (Cont’d) Function Method Address (Hex) V.32 PN Length 289, 288 (see Note 1) AGC Gain Word Round Trip Far Echo Delay Equalizer Frequency Correction Eye Quality Monitor (EQM)
  • Page 64 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 4-1. Interface Memory RAM Addresses (Cont’d) Function Method Address (Hex) CM/JM/CI Frame - See Section 9 SYNC CM/JM/CI Data Call Function Modulation 0 Modulation 1 Modulation 2 Protocol (optional) GSTN (optional) Frame End...

  • Page 65: Host Dsp Read And Write Procedures

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 4.2 HOST DSP READ AND WRITE PROCEDURES DSP RAM Write Procedure Set MEMW to inform the DSP that a RAM write will occur when MEACC is set. Load the RAM address into the MEADDH and MEADDL registers.

  • Page 66: Figure 4-1. Method 1 Example - Changing Dtmf Tone Duration (Lsb)

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide START 1 → MEMW (1D:5) 02h → MEADDH (1D:0-3) 18h → MEADDL (1C:0-7) NEW DATA → MEDAL (18:0-7) 1 → MEACC (1D:7) MEACC (1D:7) = 0 → MEMW (1D:5) 1026F4-1 Method 1 Figure 4-1. Method 1 Example - Changing DTMF Tone Duration (LSB)

  • Page 67: Figure 4-2. Method 2 Example - Changing Rts-Cts Delay

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide START NEW MSB DATA → 1 → MEMW (1D:5) MEDAL (18:0-7) 02h → MEADDH 1 → MEACC (1D:7) (1D:0-3) 02h → MEADDL (1C:0-7) MEACC (1D:7) = NEW LSB DATA → MEDAL (18:0-7) 0 → MEMW (1D:5) 1 →...

  • Page 68: Figure 4-3. Method 3 Example - Changing Tonea Threshu

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide START 1 → MEMW (1D:5) Ah → MEADDH (1D:0-3) B8h → MEADDL (1C:0-7) NEW LSB DATA → MEDAL (18:0-7) NEW MSB DATA → MEDAM (19:0-7) 1 → MEACC (1D:7) MEACC (1D:7) = 0 ? 0 →...

  • Page 69: Figure 4-4. Method 4 Example - Reading Eqm

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide START 0 → MEMW (1D:5) 2h → MEADDH (1D:0-3) 0Ch → MEADDL (1C:0-7) 1 → MEACC (1D:7) MEACC (1D:7) = 0 ? READ MEDAM (19:0-7) READ MEDAL (18:0-7) 1026F4-4 Method 4 Figure 4-4. Method 4 Example - Reading EQM...

  • Page 70: Dsp Ram Data Scaling

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 4.5 DSP RAM DATA SCALING Function 1: V.34 Transmitter Speed Acc. Method: 1 Addr.: 2E5h K56flex/V.34 Receiver Speed Acc. Method: 1 Addr.: 2E4h When connected in V.34, the current transmitter and receiver speeds may be read from 2E5h and 2E4h, respectively. These locations are updated after each handshake, retrain or rate renegotiation.
  • Page 71 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Function 2: V.32 bis and V.33 Rate Sequence Acc Method: Table 4-1 Addr. 208h-2C9h V.32 bis Rate Sequence Bits. ITU-T defines the V.32 bis rate sequence bits as follows: DATA B0 = MSB; B15 = LSB...
  • Page 72 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide V.33 Rate Sequence Bits. ITU-T defines the V.33 rate sequence bits as follows: For B14 = 0: DATA B0 = MSB; B15 = LSB Description B0-B3, B7, B11, B15 For synchronizing on the rate sequence...

  • Page 73: Table 4-2. R And E Rate Sequences - V.32 To V.32 (V32Bs = 0)

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide To modify R2, the host must wait until the RSEQ bit is set to a 1 by the DSP. The host then has 1.5 seconds to modify R2 (through address 205h, 204h). To modify R3, the host must wait until the RSEQ bit is set to a 1 by the DSP, then change R3 (through address 205h, 204h).
  • Page 74 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Functions 3-11: Dialing Parameters Acc. Method: See Below Addr.: See Below For Functions 3, 4, 7, 8, and 9, the time T (in ms) is calculated as follows: Equation: N = T x 2.4 Where: N is the decimal value of the hex number written to RAM (1-FFh).
  • Page 75 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Function 12: Transmitter Output Level Gain-All Modes Acc. Method: 2 Addr.: 3DBh, 3DAh Transmitter Output Level Gain-FSK Modes Acc. Method: 3 Addr.: B57h Transmitter Output Level Gain-All Modes (Addr. 3DBh, 3DAh) The transmitter output level gain constant (G) in dBm is calculated as follows:...

  • Page 76: Figure 4-5. News Masking Registers

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Function 13: Dual Tone 1 Frequency Acc. Method: 2 Addr.: 281h, 280h Function 14: Dual Tone 2 Frequency Acc. Method: 2 Addr.: 283h, 282h Frequency F (in Hz) is calculated as follows: Equation: N = F/0.109863 Where: N is the decimal value of the hex number written to RAM.
  • Page 77 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Function 22: Far-End Echo Frequency Offset Acc. Method: 4 Addr.: 852h Function 22 provides the far-end echo frequency offset (FO), sometimes known as phase roll, in V.34/V.32 configurations. FO = (N * SYMBOL RATE)/2 22 Equation: Where: SYMBOL RATE = 2400, 2800, 3000, 3200, or 3429 (V.34) (See Function 60.)
  • Page 78 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Function 25: Answer Tone Length Acc. Method: 2 Addr.: 229h, 228h Function 26: Silence After Answer Tone Period Acc. Method: 2 Addr.: 22Ah, 22Bh The ITU-T 2100 Hz answer tone length and silence after answer tone are calculated as follows:...

  • Page 79: Figure 4-6. Tone Detectors

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide The AGC may be disabled by first writing 0 to address 9BBh (DSRATE), then writing a 07FFh to address 8B9h (DUGAIN). The first-order low pass filter in each level detector, defined by the coefficients LPGAIN and LPFBK, controls the response time of each tone detector.
  • Page 80 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Example: A call-progress tone detector is required for the US telephone network to detect appropriate tones that exceed –35 dBm. Solution: The requirement can be met by detecting tones in the 245 Hz-650 Hz range. A bandpass filter with a passband of 245 Hz- 650 Hz must be designed.

  • Page 81: Figure 4-7. Biquad Filter And Level Detector

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide BIQUADRATIC FILTER 1 BIQUADRATIC FILTER 2 h 1 (t) h 2 (t) INPUT Σ ABS Σ ENERGY AVERAGING FILTER OUTPUT h 3 (t) THRESHOLD Σ LPGAIN COMPARATOR Notes: 1. The Prefilter is the same except for the squarer section.
  • Page 82 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Function 30: RLSD Drop Out Timer Acc. Method: 1 Addr.: 270h, 271h V.32 bis, V33, V17, V29, V27, V.26 and V.21 channel 2 Address 270, 271 holds the value for a 16-bit counter which decrements at a baud interval when energy is removed from RXA.
  • Page 83 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Function 34: V.32 PN Length Acc. Method: 2 Addr.: 289h, 288h The V.32 bis/V.32 handshake and retrain sequence may be shortened or lengthened to meet special applications by adjusting the length of the PN (TRN) sequence. The answering modem sends two TRN sequences during the handshake while the originating modem sends only one.

  • Page 84: Figure 4-8. Relationship Of Eqm To Eye Pattern

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Function 46: Eye Quality Monitor Acc. Method: 4 Addr.: 20Ch In V.32 4800 bps, V.29, V.27, V.22 bis, V.22 and Bell 212A modes, EQM is the filtered squared magnitude of the error vector. However, for all TCM modes (V.34, and V.33 modes, and V.32 12000, 9600, and 7200 bps modes), EQM is the filtered minimum trellis path length (or metric).
  • Page 85 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Function 47: Maximum Period of Valid Ring Signal Acc. Method: 1 Addr.: 21Fh Function 48: Minimum Period of Valid Ring Signal Acc. Method: 1 Addr.: 21Eh The ring detector measures the period of pulses on the ring detect input and determines whether the pulses are within the frequency range specified by the Maximum Period of Valid Ring Signal and Minimum Period of Valid Ring Signal functions.
  • Page 86 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Function 52: ITU-T CRC 32 Select Acc. Method: 1 Addr.: 0B3h(0) The type of cyclic redundancy check (CRC) generation and detection can be selected by writing to bit 0B3h:0 [0 = ITU-T CRC 32; 1 = ITU-T CRC 16 (default)].

  • Page 87: Figure 4-9. V.34 Symbol Rate Negotiation Process

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide When the MDP determines, from the bandwidth, the maximum supportable symbol rate, the MDP will enable all symbol rates below that maximum value. For example, if the line probe indicates that the bandwidth is adequate to support 3000 baud, then 2800 and 2400 baud will also be supported.
  • Page 88 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Function 65-67: Not Applicable Function 68: EQM Above Threshold Acc. Method: 1 Addr.: 133h When the high byte of the EQM reading (address 20Dh) goes above the EQM Above Threshold, the MDP will assert the EQMAT bit (0Bh:1).
  • Page 89 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Consequently, the default values written into RAM are: Address (Hex) Value (Hex) Comment Note: This 0 causes the search algorithm to use low byte of EQM The next threshold (it is equal to 00E0h) Configuring the ARAinRAM Thresholds During the V.34 Handshake...
  • Page 90 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Function 70: V.21/V.23 CTS Mark Qualify Acc Method: 1 Address: 10Dh:3 In V.21/V.23 configurations, CTS turn-on qualifying time can be controlled by writing to bit 10Dh:3 [0 = no qualifying time after Mark (default); 1 = qualifying time of 45 ±5 ms after Mark]. This bit is unaffected by the action of NEWC.
  • Page 91 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Receiver FIFO (RXFIFO) The 16-byte RXFIFO is always enabled. The 128-byte RXFIFO Extension (RXFIFOX) is controlled by writing to the Receive FIFO Extension Enable bit (701h:0) [0 = RXFIFOX disabled; 1 = RXFIFOX enabled (default)].
  • Page 92 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide RXFIFO Error Status Bits The RXFIFO includes five error status bits: BRKD (0Eh:6), SYNCD (0Ah:1), RXP (01h:0), FE (0Ah:4), and PE (0Ah:5). SYNCD is used for 7E flag detection in HDLC mode only and BRKD indicates that an asynchronous break has been received.

  • Page 93: Table 4-7. V.34 Rate Sequence Mask Bit Assignments

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Function 85: V.34 Data Rate Mask Acc Method: 2 Address: 383h, 382h K56flex/V.34 Transmitter Maximum Data Rate Mask Acc Method: 1 Address: 605h K56flex/V.34 Receiver Maximum Data Rate Mask Acc Method: 1 Address: 604h The V.34 data rate masks occupy two bytes in RAM.

  • Page 94: Table 4-8. V.34 Remote Mode Data Rate Capability Bit Assignments

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Function 87: V.34 Remote Modem Data Rate Capability Acc Method: 2 Address: 209h, 208h V.34 Remote Modem Asymmetric Data Rate Acc Method: 1 Address: 209h:7 The data rate capability of the remote modem is reflected in a binary sequence transmitted by the remote modem during Phase 4 of the handshake.
  • Page 95 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Function 100: Minimum On Time (DTMF) Acc Method: 3 Address: E96h The minimum on time is defined as the minimum period of time of the DTMF signal beginning when the signal is detected and ending when the energy is below the turn-off threshold. The on-time parameter cannot be set below 20 ms (0000h). The default on-time parameter is set for 40.0 ±1 ms.
  • Page 96 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Function 105: Frequency Deviation, Low Group (DTMF) Acc Method: 3 Address: C94h This parameter controls the acceptable frequency range for the low group DTMF tones (697, 770, 852, and 941 Hz). Increasing the value of this parameter increases the frequency range. The frequency range will vary from one DTMF symbol to another.

  • Page 97: Hdlc Operation

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 5. HDLC OPERATION The HDLC (High Level Data Link Control) protocol is a standard procedure used for data communications. SDLC (Synchronous Data Link Control) is a bit-oriented protocol which is a subset of HDLC. The same format is used in both protocols although all SDLC fields must be eight-bit octets.

  • Page 98: Operation

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide FLAG ADDR CONTROL INFORMATION FCS FLAG FRAME STARTS FRAME ENDS 1026F5-1 HDLC Frm Figure 5-1. HDLC Frame Frame Check Sequence The purpose of the Frame Check Sequence (FCS) is to give a shorthand representation of the entire transmitted information field and to compare it to the identically generated shorthand representation of the received sequence.

  • Page 99: Transmitter Hdlc Operation

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 5.2.2 Transmitter HDLC Operation The format of the data input to the MDP is in groups of 8-bit bytes. As in the normal synchronous parallel data mode, the least significant bit of the byte is transmitted first.

  • Page 100: Example Application

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide After the FCS transmission (immediately following bit x0), one flag is sent to signify the end of the current frame and the beginning of the next frame. After the final zero in a flag is transmitted, the MDP looks to see if the host has loaded new data into TBUFFER.

  • Page 101: Receiver Example

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 5.3.3 Receiver Example The steps to perform a typical HDLC reception are (Figure 5-2b): Set the MDP configuration in CONF; reset the ASYN bit; set the HDLC bit. Then monitor, through interrupts, the RDBF, OE, SYNCD, PE, and FE status bits.

  • Page 102: Figure 5-2. Hdlc Signal Timing

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide TRANSMIT FLAG FLAG DATA 1 DATA 2 DATA 3 FLAG DATA 1 DATA 2 CONTINUOUS ONES FLAG DATA TDBE FLAGS CRCS MHLD 1. The host enters HDLC mode by setting HDLC bit. 2. The modem sets FLAGS prior to sending the first bit of the first 7E flag.

  • Page 103: Host Functions

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 6. HOST FUNCTIONS 6.1 INTERRUPT REQUEST HANDLING DSP interface memory registers 00, 10, 1E, and 1F have unique hardware connections to the interrupt logic. Register 00 is the Receive Buffer (RBUFFER) and register 10 is the Transmit Buffer (TBUFFER). Registers 1E and 1F hold interrupt flag, interrupt enable, and interrupt active bits.

  • Page 104: Table 6-1. Interrupt Request Bits

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 6-1. Interrupt Request Bits Interrupt Interrupt Interrupt Active Enable Flag Interrupt Condition Description Interrupt Clear Procedure NSIA NSIE NEWS New status detected (NEWS transitioned from a Host writes a 0 into NEWS 0 to 1)

  • Page 105: Figure 6-1. Auto Dial Sequence And Dial Digits

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide DIal Digits/Tone Pairs START Tone Pairs Dial Digit Tone 1 Tone 2 1336 1 → RA (07:1) 1209 ACTIVATE OHRC 1336 0 → RTS (08:0) 1477 1209 1336 81h → CONF (12:0-7) 1 → NEWC (1F:0)

  • Page 106: Figure 6-2. Host Flowchart - Originating Automode

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Monitor Signals ANS detected 1300 Hz and 1650 Hz and AC only USB1 or 2225 Hz ANSAM for Qualify_Answer FSK allowed FSK allowed detected detected detected length of time V.23 V.21 V.32 AUTO = 0...

  • Page 107: Figure 6-3. Host Flowchart - Answering Automode

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Automoding from V.8 Automoding from V.32 Send V.25 Answer Tone Send ANSAM Monitor V.32 AA Monitor V.8 CM & V.32 AA V.32 AA Done Sending Done Sending V.32 AA detected detected detected V.32 V.32...

  • Page 108: Modem Self-Test Information

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 6.4 MODEM SELF-TEST INFORMATION After a power-on reset, the MDP performs a self-test of the internal controller and DSP devices. After each self-test, the test results and configuration information is loaded into interface memory.

  • Page 109: Figure 6-4. Modem Self-Test Results Read Procedure

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Power-On Reset Valid RAM1 and RAM2 checksums in registers 1A-1D? Read controller self-test information Controller self-test results available for 5 ms Read Register 10 to clear 1E:3 and discard value 1E:3 = 1? Read DSP self-test...

  • Page 110: Eqm Averaging

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 6.5 EQM AVERAGING A host-programmable EQM averaging feature helps the host controller with retrain and rate change decisions. A single-pole low-pass filter is used to average the EQM samples. The number of symbol intervals between EQM samples is host- programmable in memory location 26Bh ( EQMBaudInterval ).

  • Page 111: Retrain And Automatic Rate Change

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 6.6 RETRAIN AND AUTOMATIC RATE CHANGE This section explains how to perform the retrain and rate change. 6.6.1 Retrain Without a Rate Change K56flex/V.34/V.32/V.32 bis and V.22 bis Configurations When the RTRN bit is set to a 1, the MDP will initiate the retrain sequence. The modem which detects the retrain sequence will respond with training, and both modems will proceed with the proper training sequence.

  • Page 112: Cleardown

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 6.8 CLEARDOWN 6.8.1 K56flex Cleardown Sourcing a K56flex Cleardown Request The host loads CONF with 90h. The host sets RREN to 1 Receiving a K56flex Cleardown Request On receiving a Cleardown request, the MDP responds by writing 96h into the ABCODE register and also writing C0h into the CONF register.

  • Page 113: Design Considerations

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 7. DESIGN CONSIDERATIONS Good engineering practices must be adhered to when designing a printed circuit board (PCB) containing the MDP. Suppression of noise is essential to the proper operation and performance of the MDP itself and for surrounding equipment.

  • Page 114: Table 7-1. Modem Pin Noise Characteristics

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 13. Provide a 0.1 µF ceramic decoupling capacitor to ground between the high frequency filter and the +5VA pin. 14. Provide a 0.1 µF ceramic decoupling capacitor to ground between the +5V supply and the +5VD pin.

  • Page 115: Electromagnetic Interference (Emi) Considerations

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 7.2 ELECTROMAGNETIC INTERFERENCE (EMI) CONSIDERATIONS The following guidelines are offered to specifically help minimize EMI generation. Some of these guidelines are redundant with, or similar to, the general guidelines but are mentioned again to reinforce their importance.
  • Page 116 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Telephone and Local Hand Set Interface Place common mode chokes in series with Tip and Ring for each connector. Decouple the telephone line cables at the telephone line jacks. Typically, use a combination of series inductors, common mode chokes, and shunt capacitors.

  • Page 117: Crystal Specifications

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 7.3 CRYSTAL SPECIFICATIONS Recommended crystal specifications are listed in Table 7-2. Table 7-2. Crystal Specifications - 56.448 MHz Characteristic Value Value Rockwell Part No. 333R45-011 5333R02-017 Electrical Frequency 56.448 MHz nom. 56.448 MHz nom.

  • Page 118: Recommended Interface Circuits

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 7.4 RECOMMENDED INTERFACE CIRCUITS The recommended interface connections to the MDP are shown Figure 7-1 (144-pin TQFP). A typical external circuit for connection to the line with no external hybrid and a transmit level to -7 dBm is shown in Figure 7- A typical external circuits for connection to the line with an external hybrid and a transmit level to 0 dBm is shown in Figure 7-3.

  • Page 119: Figure 7-1. Interface Schematic - 144-Pin Tqfp

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 4.7µH YCLK XCLK XTLI SYCLK 15pF 10pF 56.448 MHz XTLO 10pF 5% ~RLYA ~RLYB RINGD TELEPHONE LINE/ TXA1 EXTERNAL TELEPHONE/ TXA2 AUDIO TELIN INTERFACE TELOUT MICV MICM ~WRITE ~READ SPKMD MICBIAS MCU: IRQ ~SET3V...

  • Page 120: Figure 7-2. Typical Line Interface

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide ~OHRC (NOTE 2) (NOTE 2) 1/4W 1N4148 TXA1 10 uF 40.2K (NOTE 1) 4.3V RING .001 uF 6.8 uF 2N2222 1/4W 2N2102 18.7K 4.3V HLL5243B D2–D5: 1N4003 TXA2 VR1: V150LA10A NOTES: 1. CHOOSE R1 VALUE TO OBTAIN 600 OHM INTERNAL IMPEDANCE.

  • Page 121: Figure 7-4. Typical External Speaker Circuit

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 0.1 uF SPKM LM386 50 OHM SPEAKER 1061F7-5 Sch Spkr Figure 7-4. Typical External Speaker Circuit 1119...

  • Page 122: Package Dimensions

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 7.5 PACKAGE DIMENSIONS The 144-pin TQFP package dimensions are shown in Figure 7-5. PIN 1 DETAIL A Millimeters Inches* Dim. Min. Max. Min. Max. 1.6 MAX 0.0630 MAX 0.05 0.15 0.0020 0.0059 1.4 REF 0.0551 REF...

  • Page 123: Implementation

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 8. T.30 IMPLEMENTATION 8.1 GENERAL ITU-T Recommendation T.30 details procedures for facsimile transmission over the PSTN. This standard describes how to initiate, complete, and end a fax transmission. This section describes methods to set up host software to implement T.30 with the modem.

  • Page 124: Phase C

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide resolution, coding scheme (Modified Huffman, Modified Read), recording width, recording length, and minimum scan line time. The calling unit then responds with a Digital Command Signal (DCS) which informs the called unit which options are chosen to complete this facsimile call.

  • Page 125: Figure 8-1. Basic Block Diagram Of G3 Facsimile

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide The error detection is performed by comparing the CRC or FCS. Using ECM, the fax data rate can be as fast as 14400 bps, therefore, the host microprocessor may not be able to keep up if implementing HDLC without the use of a serial I/O device.

  • Page 126: Figure 8-2. G3 Facsimile Procedure

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide CALLING UNIT CALLED UNIT CALLING TONE: 1100 Hz, 0.5S ON/3S OFF CALLING TONE: INDICATE NON-SPEECH TERMINAL CALLED STATION ID: 2100 Hz, 2.6S <ON <4S PHASE A DIGITAL ID SIGNAL: 300 BPS FSK, HDLC FORMAT DIGITAL COMMAND SIGNAL: 300 BPS FSK, HDLC FORMAT TRAINING CHECK: HIGH SPEED TRAIN FOLLOWED BY 1.5S OF ZEROS...

  • Page 127: Figure 8-3. Originating A Fax Call - General

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide FAX ORIGINATE DIAL RECEIVE DIS FRAME NOTE: THE ABORT TIMER IS USED TO SET UP ABORT TIMER SEND DCS FRAME NOTE: TIME OUT THE CONNECTION ATTEMPT. SET UP CALLING TONE ON/OFF SEND TCF SIGNALS TIME AND V.21 FLAG DETECT...

  • Page 128: Figure 8-4. Originating A Fax Call - Phase A

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide SET UP CALLING TONE ON/OFF SEND 1100 Hz TIME AND V.21 CNG TONE FLAG DETECT CONFIGURE FOR DTMF GENERATION 81h → CONF (12:0-7) 1 → DTMF (9:5) 1 → ORG (9:4) TDBE (1E:3) = 1? 1 →...

  • Page 129: Figure 8-5. Originating A Fax Call - Phase B

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide RECEIVE SEND TCF SIGNALS DIS FRAME NOTE: DATA TO BE RECEIVED RECEIVE FSK/HDLC HIGH SPEED NOTE: SHOULD BE A DIS FRAME. SIGNALS CONFIGURATION SET UP 1.5 SECOND RETURN TIMER 1 → RTS (8:0) SEND...

  • Page 130: Figure 8-6. Originating A Fax Call - Phase C

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide TRANSMIT MESS HIGH SPEED CONFIGURATION 1 → RTS (8:0) TDBE = 1? LOAD DATA INTO TRANSMIT BUFFER XXh → TBUFFER (10:0-7) MORE TO TRANSMIT? RETURN 1026F8-06 Orig C Figure 8-6. Originating a Fax Call - Phase C...

  • Page 131: Figure 8-7. Originating A Fax Call - Phase D

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide SEND EOM FRAME TRANSMIT FSK/HDLC SIGNALS NOTE: THE FRAME TO BE LOADED NOTE: AND TRANSMITTED IS THE NOTE: EOM FRAME. RETURN RECEIVE MCF FRAME RECEIVE FSK/HDLC NOTE: DATA TO BE RECEIVED NOTE: SHOULD BE AN MCF FRAME.

  • Page 132: Figure 8-8. Answering A Fax Call - General

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide AUTOANSWER DATA/FAX DETECTION NOTE 1: CLEAR VARIABLE VARIABLE "CONNECT" SETS TO A 1 SEND DIS FRAME "CONNECT" IF CONNECTION IS ESTABLISHED (RLSD TURNS ON) 1 → RA (7:1) RECEIVE DCS FRAME NOTE: DIS, DCS, TCF, CFR, MESS, FTT, EOM, AND MCF ARE FRAMES SPECIFIED BY CCITT T.30 SPECIFICATION.

  • Page 133: Figure 8-9. Answering A Fax Call - Phase A (Cng)

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide TONEA (B:7) = 1? SET UP TO DETECT 1100 Hz FAXCALLING TONE (CNG) TIME OUT DELAY 600 MS 3 SECONDS CONFIGURE FOR TONE MODE 80h → CONF (12:0-7) TONEA = 0? 1 → NEWC (1F:0) DELAY 3.2 SEC...

  • Page 134: Figure 8-10. Answering A Fax Call - Phase A (Ced)

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide GENERATE 2100 Hz FAX ANSWER CALLED TONE (CED) GENERATE 2100 Hz CONFIGURE TONE MODE CED TONE FOR 2100 HZ WRITE TO RAM (METHOD 2) NOTE: THE MODEM WAS PREVIOUSLY CONFIGURED FOR TONE GENERATION 4AABh → 281, 280 MODE (CONF = 80h).

  • Page 135: Figure 8-11. Answering A Fax Call - Phase B

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide SEND RECEIVE DIS FRAMES DCS FRAME NOTE: THE FRAME TO BE LOADED NOTE: DATA TO BE RECEIVED TRANSMIT FSK/HDLC RECEIVE FSK/HDLC AND TRANSMITTED IS THE SHOULD BE A DCS FRAME. SIGNALS SIGNALS DIS FRAME.

  • Page 136: Figure 8-12. Answering A Fax Call - Phase C

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide RECEIVE MESS HIGH SPEED CONFIGURATION RLSD = 1? RDBF = 1? READ RECEIVE BUFFER RBUFFER → XXh DETECT 6 CONSECUTIVE EOLS? RLSD = 0? RETURN 1026F8-12 Ans C Figure 8-12. Answering a Fax Call - Phase C...

  • Page 137: Figure 8-13. Answering A Fax Call - Phase D

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide RECEIVE EOM FRAME LOW SPEED CONFIGURATION NOTE: DATA TO BE RECEIVED RECEIVE FSK/HDLC SHOULD BE A EOM, MPS, OR SIGNALS PRI-Q FRAME. RETURN SEND MCF FRAMES NOTE: THE FRAME TO BE TRANSMIT FSK/HDLC LOADED AND TRANSMITTED SIGNALS IS THE MCF FRAME.

  • Page 138: Figure 8-14. Transmitting Fsk/Hdlc Signals

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide TRANSMIT FSK/HDLC SIGNALS LOW SPEED CONFIGURATION TRANSMIT PREAMBLE TRANSMIT PARALLEL DATA FLAGS (0A:1) = 1? WAIT 90 MS 0 → RTS (08:0) RETURN 1026F8-14 FSK Figure 8-14. Transmitting FSK/HDLC Signals 8-16 1119...

  • Page 139: Figure 8-15. Low Speed Configuration Routine

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide LOW SPEED CONFIGURATION CONFIGURE FOR V.21 CHANNEL 2 FSK A8h → CONF (12:0-7) 1 → NEWC (1F:0) NEWC = 0? SET UP FOR PARALLEL DATA, HDLC, AND DATA BITS 1 → TPDM (08:6) 1 → HDLC (06:4) 1 →...

  • Page 140: Figure 8-16. Transmit Preamble Routine

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide TRANSMIT PREAMBLE 1 → RTS (8:0) CTS (F:5) = 1? NOTE: THE MODEM SENDS 1 DELAY 1 SECOND SECOND OF HDLC FLAGS (7Eh OR 01111110). RETURN 1026F8-16 Tx Pream Figure 8-16. Transmit Preamble Routine...

  • Page 141: Figure 8-17. Transmit Parallel Data Routine

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide TRANSMIT PARALLEL DATA NOTE: COUNT NUMBER OF INITIALIZE BYTE BYTES IN HDLC FRAME TO COUNT BE SENT. TDBE = 1? LOAD DATA INTO TRANSMIT BUFFER XXh → TBUFFER (10:0-7) DECREMENT BYTE COUNT WHEN BYTE COUNT = 0, THERE...

  • Page 142: Figure 8-18. Receive Fsk/Hdlc Signals

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide RECEIVE FSK/HDLC SIGNALS RLSD (0F:7) = 1? RDBF (1E:0) = 1? READ RECEIVE BUFFER RBUFFER (0:0-7) → XXh SYNCD (0A:0) = 1? READ DATA PER HDLC DESCRIPTION IN SECTION 5 NOTE: WAIT FOR RLSD = 0 TO INDICATE END OF FRAME.

  • Page 143: Figure 8-19. High Speed Configuration Routine

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide HIGH SPEED CONFIGURATION CONFIGURE FOR HIGH SPEED NOTE: CONFIGURE FOR THE SPEED SPECIFIED BY THE B1h → CONF (V.17 14400) DCS FRAME FROM THE 14h → CONF (V.29 9600) CALLING MODEM. 12h → CONF (V.29 7200) 02h →...

  • Page 144: Ecm Frame Structure

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 8.2.2 ECM Frame Structure In Error Correction Mode, one frame of facsimile data consists of 256 or 64 octets of data. Each page may contain 1 to 256 frames. Also, 1 to 256 pages may be transmitted. The ECM frame structure is illustrated in Figure 8-22. Following the high speed training sequence, the flag, address field, and control field is transmitted.

  • Page 145: Figure 8-20. Hdlc Frame Structure

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide PREAMBLE BINARY CODED INFO NSF FRAME CSI FRAME DIGITAL ID FRAME (OPTIONAL) (OPTIONAL) (MANDATORY) FLAG ADDRESS CONTROL FLAG 01111110 11111111 1100X000 01111110 8 BIT 8 BIT 8 BIT 8 BIT 32 BIT 16 BIT 8 BIT FCS: FRAME CHECK SEQUENCE;...

  • Page 146: Figure 8-21. Phase C Format

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide RETURN TO CONTROL (RTC) INDICATING END OF DOCUMENT TRANSMISSION FORMAT: SIX CONSECUTIVE EOLS. START OF PHASE C DATA DATA FILL DATA ≥ T ≤ T ≥ T T MINIMUM TRANSMISSION TIME OF A TOTAL CODED SCAN LINE.

  • Page 147: Figure 8-22. Ecm Frame Structure

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide ADDRESS FRAME EOL, TAG, FIELD NUMBER ALIGN BITS FLAG CONTROL FACSIMILE FLAG FIELD DATA CHECK TRAINING 200 MS 7E 256* OCTETS OF DATA PAD BITS 1 FRAME OF DATA FACSIMILE CODED DATA BLOCK (FCD)

  • Page 148: Figure 8-23. Ecm Message Protocol Example

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide MESSAGE, PAGE 0, BLOCK 0 PPS-NULL (TO INDICATE MORE BLOCKS FOR THIS PAGE WILL BE TRANSMITTED) PPR (TO IDENTIFY FRAMES RECEIVED WITH ERRORS) RETRANSMIT MESSAGE FRAMES IN ERROR, PAGE 0, BLOCK 0 PPS-NULL MCF (TO INDICATE NO ERRORS, AND READY TO RECEIVE)

  • Page 149: Figure 8-24. Pps And Ppr Frame Structure

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide FCF1 FCF2 PAGE BLOCK TOTAL # COUNT COUNT OF FRAMES (0-255) (0-255) IN BLOCK (1-256) FSK 300 BPS = FLAG = ADDRESS FIELD = CONTROL FIELD FCS = FRAME CHECK SEQUENCE PPR FRAME STRUCTURE...

  • Page 150: Figure 8-25. Fsk Signal Recognition Algorithm

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide START HIGH SPEED CONFIGURATION (0F:6) = 1? INITIALIZE AND START TIMER1 FLAGDT (0A:6) = 1? INITIALIZE AND START TIMER2 PNSUC (0A:7) = 1? FLAGDT (0A:6) = 1? PNSUC (0A:7) = 1? TIMER2 ≥ 100 MS TIMER1 ≥...

  • Page 151: Operation Considerations

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 9. V.8 OPERATION CONSIDERATIONS The host can access several registers in RAM to control and monitor V.8 operation (see Section 4). There are five control registers (Table 9-1) and three status registers (Table 9-2). The host also has access to 13 registers which contain the configuration (CONF) codes associated with the 13 modes of operation (Table 9-3).

  • Page 152: Table 9-1. V.8 Host Control Bits

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide zero. On the other hand, if the call function is allowed, the answer modem will respond with the same call function as that received in CM. JM will contain all the necessary modulation octets needed to reflect the jointly common modulation modes available at the answer modem and received in the CM sequence.

  • Page 153: Table 9-3. Modulation Modes

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 9-3. Modulation Modes Default Address Value (Hex) Configuration (Hex) 1 K56flex Receive V.34 full-duplex V.32 bis V.22 bis V.17 V.29 V.27 V.26 ter V.26 bis V.23 full-duplex (Note 2) V.23 half-duplex V.21 Notes: See CONF codes in Table 3-1.

  • Page 154: And Automode

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 9-6. JM Frame Address Octet (Hex) Preamble SYNC JM Call Function from CM Common modulation 0 Common modulation 1 * Common modulation 2 * Protocol (optional) GSTN (optional) Frame End * if necessary Table 9-7.

  • Page 155: Handshake Monitoring

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 9.4 HANDSHAKE MONITORING 9.4.1 V.8 Octet Monitoring During the V.8 (Phase 1) procedure the received V.8 octets can be read from the interface memory RBUFFER register by clearing bit 305h:3 in the V.8 host control bits. The procedure is the same as accessing receive data during normal data mode.

  • Page 156: Table 9-10. Transmitter Handshake Phase And States

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 9-10. Transmitter Handshake Phase and States Register (Hex) Transmitter Handshake Phase Transmitter Handshake Phase State (SECTXB) Bits 7-5: Transmitter Handshake Phase Bit 7 Bit 6 Bit 5 Handshake Phase (ITU Specification) Value Phase 1 (V.8) Phase 2 (V.34)

  • Page 157: Figure 9-1. Phase 2 Receiver States

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide The phase state value is shown above or below the signal trace. Figure 9-1. Phase 2 Receiver States The phase state value is shown above or below the signal trace. Figure 9-2. Phase 2 Transmitter States...

  • Page 158: Figure 9-3. Phase 3 States

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide The phase state value is shown above or below the signal trace. Figure 9-3. Phase 3 States The phase state value is shown above or below the signal trace. Figure 9-4. Phase 4 States...

  • Page 159: V.8Bis

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 10. V.8bis 10.1 V.8bis TRANSMITTER V.8bis tones can be transmitted from tone mode (CONF = 8Xh), speakerphone mode (CONF = ACh), or V.21 mode (CONF = A0h). CEQ should be 0. The V8bis tones are sent in the same manner as DTMF tones, i.e., write the codeword into TBUFFER when TDBE=1.
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  • Page 161: Adpcm Voice Compression And Decompression

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 11. ADPCM VOICE COMPRESSION AND DECOMPRESSION ADPCM compression (Rx-coding) of received, ADC digitized voice may be selected to minimize the memory required for message storage. Silence detection and deletion may also be selected to further reduce the memory storage requirements.

  • Page 162: Figure 11-1. Adpcm Rx-Coder

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 11-1. ADPCM Voice Mode Selection CONF CDEN DCDEN Mode Tx Pass-through Voice Mode Tx ADPCM Voice Mode Rx Pass-through Voice Mode Rx ADPCM Voice Mode NOTES: * = ACh, 80h, 81h, 83h, or 86h.

  • Page 163: Figure 11-3. Rx-Coder Operation

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Start Initialize 1 → TXSQ ACh → CONF 0 → CEQ 1 → CDEN NOTE: Reset CDEN = 0 for X → CODBITS 16-bit pass-through voice mode. 1 → RXV 0 → TXV 1 → NEWC...

  • Page 164: Figure 11-4. Tx-Decoder Operation

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Start Initialize 0 → TPDM ACh → CONF 0 → CEQ 1 → DCDEN X → DECBITS 0 → RXV NOTE: Reset DCDEN = 0 for 1 → TXV 16-bit pass-through voice mode. 1 → NEWC 0 →...

  • Page 165: Voice Agc

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 11.3 VOICE AGC An optional AGC function in included in the voice receiver (compressed and uncompressed). Voice AGC is enabled or disabled by setting or resetting the VAGC bit [04h:2 (shared with NRZIE)]. The AGC is updated on a 28-sample “voice frame” basis. The average input sample (AverageENG) is compared to a voice threshold (VTHRESH) to determine if there is enough energy to perform the automatic gain control (AGC).
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  • Page 167: Simultaneous Audio/Voice And Data (Audiospan)

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 12. SIMULTANEOUS AUDIO/VOICE AND DATA (AUDIOSPAN) All RAM addresses mentioned in this section are 16-bit access if 12th bit of address field is set, or 8-bit access if 12th bit is reset, unless otherwise specified.

  • Page 168: Ml144 Mode Selection

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Maximum Voice+Data Rate (Address 42Ah) Bits 7:5 Reserved Bit 4 Remote Tx Silence Detection Enable/Disable Enable remote Tx silence detection. Disable remote Tx silence detection. Bit 3 Reserved Bits 2-0 Maximum Voice+Data Rate 000 = 4800 bps.

  • Page 169: Ml144/V.61 Audiospan Rate Sequence

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Tone 1 Amplitude (Address AB0) and Tone 2 Amplitude (Address AB2h) The power equation is: Po/20 N = 2033(10 Where: N is the decimal equivalent of the hex number written to RAM an Po is the power level in dBm.

  • Page 170: Selecting Voice+Data Rates

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Tx Rate Sequence Word 3: Low Byte Address (430h, Default = 93h); High Byte Address (431h, Default = 01h) Rx Rate Sequence Word 3: Low Byte Address (434h); High Byte Address (435h) High Byte (Address 431h/435h) Definition...

  • Page 171: Speaker Attenuation/Gain Control

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 12.1.9 Speaker Attenuation/Gain Control Speaker Gain Control The speaker gain may be controlled through the VOLUME bits (01h:7-6): Speaker Attenuation (dB) Value in 01h:7-6 (Bin) Speaker off 0 dB (high volume) 6 dB (medium volume) 12 dB (low volume) The speaker gain may also be altered through address 990h.

  • Page 172: Telin/Telout Gain Control

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide The gain may also be altered through address B7Eh. This location is reset to default after a RREN and is adjustable only when the modems are connected. The total input gain should not bring the input signal level above -16 dBm to avoid input saturation.

  • Page 173: Host Interface Selection And Setup

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 12.2 HOST INTERFACE SELECTION AND SETUP There are basically three audio interface possibilities: Microphone/Speaker (Mic/SPKR): Where an external microphone and speaker is used. Ties into the MICV and SPKR-V pins. Headset: Where a headset with built-in microphone or an external audio source and speaker is used. The external audio source can be in the form of a microphone, CD or DAT player.
  • Page 174 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Assuming one scenario at a time: Scenario 1: User Picks Up the Handset When the handset is picked up (LCS is detected), the user wants an audio link, therefore, the handset configuration should be initiated and bit 400h:2 (voice squelch) should be reset. This causes bit 419h:7 on the remote modem to turn off.

  • Page 175: Speakerphone Configuration

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 13. SPEAKERPHONE CONFIGURATION The Speakerphone Configuration Code (CONF) is ACh. To configure for speakerphone operation: Set CONF = ACh. Set SP/HS = 1. Reset MuteSp and MuteMic. Adjust VMicLVL and VOLUME bit fields as desired.

  • Page 176: Voice Paths

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide In dual tone mode, RTS is used to control the line dual tone transmitter and DTR is used to control the speaker tone transmitter. The equations for the frequency and power values are: Frequency: N = F/0.109863...

  • Page 177: Figure 13-1. Voice Flow Block Diagram

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Data FROM Host TBUFFER,SP17 DECODE BITS [SP06:1,0] SDCDE [SP02:3] DSP Loopback DCDEN [SP02:5] 2 Bits [00] A D P C M C T L : $ A RVLB [SP01:3] 3 Bits [01] T X O U T P U T...

  • Page 178: Figure 13-2. Transmit Voice Paths

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide MLinDisable MLinOut [3E0:7,6] [3E1:3] MIC_M [10] TXA1 [00] RIN [01,11] TXA2 S R 4 O B VOLUME [SP01:7,6] MSpkDisable MSpkOut [3E0:5,4] [3E1:2] Squelch [00] RIN [00] 0 dB [10] [10] SPK_M -6 dB [01]...

  • Page 179: Figure 13-3. Receiver Voice Paths

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide RecPath [3E1:4=1] SR3IB Modem Mic Gain [SP14:1,0] 0 dB [00] 10 dB [01] MIC_M 15 dB [10] RecPath [3E1:5=1] 20 dB [11] RecPath [43E:0=0] M O D E M 1 0 4 8 8 I A...
  • Page 180 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Voice Output Path (Address 3E0h) Modem IA Line Output Modem IA Spkr Output Voice IA Line Output Voice IA Spkr Output Bits 7-6 Modem IA Line Output SR4OB to TXA1/TXA2 RIN to TXA1/TXA2 MICM to TXA1/TXA2...
  • Page 181 RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Voice Control (Address 3E1h) EnVMIC EnTELIN EnMMIC EnRIN MLinDis MSpkDis VLinDis VSpkDis Bit 7 Enable the Voice Mic Input, MICV (EnVMIC) 1 = Enable 0 = Disable Bit 6 Enable the Voice Line Input, TELIN (EnTELIN) 1 = Enable TELIN input.

  • Page 182: Volume And Microphone Level Control

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 13.2.2 Volume and Microphone Level Control Volume Control (01h:7-6) The VOLUME bits (01h:7-6) control the Voice and Modem speaker volume. Squelch 6 dB attenuation 0 dB attenuation 12 dB attenuation Voice Microphone Level Control (13h:1-0) The VMicLVL bits (13h:1-0) control the Voice mic level.

  • Page 183: Room Monitor" Mode

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 13.2.5 “Room Monitor” Mode To operate in “room monitor” mode: Set CONF = ACh. Set RXV = 1. Select the output to TXA1/TXA2 to come from SR4OB (3E0h). Setup the voice IA mic level to 20 dB gain (14).
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  • Page 185: K56Flex Setup And Code Changes

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 14. K56flex SETUP AND CODE CHANGES This section describes the configuration procedure for K56flex and provides a general description of the K56flex handshake. All RAM accesses are 8 bit (Method 1) unless otherwise noted.

  • Page 186: Table 14-1. K56Flex Data Rate Versus Configuration And Data Rate Mask Values

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 14-1. K56flex Data Rate Versus Configuration and Data Rate Mask Values Data Rate for CONF = CX Data Rate for CONF = 9X Rate Mask 605h or 604h = 0Xh Rate Mask 605h or 604h = 0Xh...

  • Page 187: K56Flex Bit Definitions

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 14.1.3 K56flex Bit Definitions 39Bh:7 - A-law / µ-law Selection . When set, A-law is enabled; when reset, µ-law is enabled. If the modems are configured opposite of each other, they will automatically fall back to V.34.

  • Page 188: Detecting K56Flex

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Client States During Phase 3 (answer & originate mode) SECTXB = 40,44,45,46,47,48 SECRXB = 30,31,32,33,48 Client States During Phase 4 (answer & originate mode) SECTXB = 62,63,64,65,66,67 SECRXB = 61,62,63,65,68 Server States During Phase 2 (answer & originate mode)

  • Page 189: Retrains And Renegotiations

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide For more flexibility, the user may prefer to take control over the data rate selection by monitoring EQM during phase 4 and manually selecting the data rate based on predetermined EQM thresholds. Such a method is used in V.34 mode with the RCV288DPx and RC336ACF/DPFL V.34 data pumps.

  • Page 190: Changes To Ram Addresses

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide Table 14-3. ARA Values Address 2E3h Value (Corresponding Symbol Rate in Baud) (Hex) 5 (3429) 4 (3200) 3 (3000) 2 (2800) 0 (2400) Table 14-4. Speed Selection Desired Speed If EQM (hex) is between...

  • Page 191: Rcv56Dpfl/Sp Downloading

    RCVDL56DPFL/SP, RCV56DPFL/SP, and RCV336DPFL/SP Designer’s Guide 15. RCV56DPFL/SP DOWNLOADING To be added. 1119 15-1...
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  • Page 193 INSIDE BACK COVER NOTES...
  • Page 194 REGIONAL SALES OFFICES US Northwest Office Europe North Japan Rockwell Semiconductor Systems Rockwell Semiconductor Systems, Ltd. Rockwell Int'l Japan Co., Ltd. US Northwest Office Berkshire Court Shimomoto Bldg Headquarters US Southwest Office 3600 Pruneridge Avenue Western Road 1-46-3 Hatsudai, Shibuya-ku...

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