HP 53150A Series Programming Manual page 71

Microwave frequency counter
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NOTE
Chapter 3 Programming Your Counter for Remote Operation
Status Reporting
Table 3-5. Standard Event Status Register
BIT WEIGHT SYMBOL DESCRIPTION
0
1
OPC
1
(RQC)
2
4
QYE
3
8
DDE
4
16
EXE
5
32
CME
6
(URQ)
7
128
PON
A detailed description of each bit in the Standard Event Status Register
follows:
Bit 0 (Operation Complete) is an event bit which is generated in
response to the *OPC command. This bit indicates that the Counter
has completed all pending operations (the pending operation condition
has transitioned from TRUE to FALSE).
If AVERage:STATe is OFF, the command INIT;*OPC sets the OPC bit
once the instrument completes a measurement; if AVERage:STATe is
ON, the command INIT;*OPC sets the OPC bit once the instrument
completes a measurement consisting of AVERage:COUNt
measurements.
The OPC bit is not in any way affected by the *OPC? query.
Bit 1 is not used.
Bit 2 (Query Error) is an event bit which indicates that either 1) an
attempt was made to read the Output Queue when it was empty or 2)
data in the Output Queue has been lost.
Programming Guide
Operation Complete
Not used because this instrument cannot request
permission to become active IEEE 488.1 controller-in-
charge.
Query Error
Device-Specific Error
Execution Error
Command Error
Not used, because this instrument does not define any
local controls as "User Request" controls.
Power On
3-31

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