Timing Of Host Interface (Dma Multi) - Toshiba SD-R5112 Product Specification

6.2.3.Timing of Host Interface (DMA Multi)

Figure 11 shows the Host Interface DMA multi word Timings
DMARQ
DMACK-*1
DIOR-/DIOW-*1
Read
DD0-15
Write
DD0-15
*1: In all timing diagrams, the low line indicator negated, and the upper line
indicators asserted.
Multi word DMA
timing parameters min(ns) max(ns)
Cycle time
t0
DMACK to DMREQ delay
tC
DIOR-/DIOW-
tD
DIOR- data access
tE
DIOR- data hold
tF
DMACK- to tristate
tZ
DIOR/DIOW- data setup
tG
DIOW- data hold
tH
DMACK to DIOR-/DIOW- setup
tI
DIOR-/DIOW- to DMACK hold
tJ
DIOR- negated pulse width
tKr
DIOW- negated pulse width
tKw
DIOR- to DMREQ delay
tLr
DIOR- to DMREQ delay
tLw
Figure 11 Host Interface Timing (DMA Multi)
t0
tD
tI
tE
tF
tH
tG
16-bit
17/29
tL
tK
Min time (ns)
120
70
5
20
10
0
5
25
25
tJ
tZ
Max time (ns)
---
---
25
35
35
SD-R5112 Rev.1.0