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D-NE500/NE506CK
5-4. BLOCK DIAGRAM — CD SECTION —
OPTICAL PICK-UP
BLOCK
(DAX-25E)
DETECTOR
RF
A
B
E
F
OPSTB
OPGSW
IC401 (1/2)
VCC
VCC3
COIL/MOTOR DRIVER
F+
46
FO1
FI1 48
FOCUS
COIL
F–
44
RO1
RI1 49
T+
42
FO2
FI2 50
TRACKING
COIL
T-
40
RO2
RI2 51
LD
LD
78
VLGO4
PD
PD
97
PAPC
S+
38
FO3
FI3 52
M602
M
SLED
S-
MOTOR
36
RO3
RI3 53
30
U
M601
32
V
SPINDLE
M
MOTOR
34
W
APWM 27
26
COM
FG 22
25
UI
24
VI
23
WI
XBRK 21
SYNC 5
DATA 8
CLOCK 7
10 13 12 52
• Signal path
: CD PLAY
•R-ch is omitted due to same
as L-ch.
IC601
DIGITAL SIGNAL PROCESSOR,
DIGITAL SERVO PROCESSOR
RFAC
84
SELECT
RFDC
88
A
92
B
91
E
89
SIGNAL
F
PROCESSOR
90
BLOCK
SERVO
FOK
65
MEMORY
BLOCK
CONTROL,
BUS BOOST
BLOCK
FFDR
96
FRDR
95
TFDR
98
TRDR
97
SFDR
100
SRDR
99
104
C176
MDP
103
IC403
MDS
102
SDTO
21
CLOCK
20
SENS
22
23 24 27 32 69
28 25
IC801 (1/2)
SYSTEM CONTROL
58
84 83 85
87 88 86 28 53
4 7
PCMD_O
PCMD
108
4
LRCK_O
LRCH
106
1
BCK_O
BCK
110
2
PCMD_I
PIO
109
15
LRCK_I
PI2
107
14
BCK_I
PI3
111
13
XRDE
PF4
18
12
IC602
DRAM
D0-D3
D0-D3
4
A0-A10
A0-A10
11
XRAS
1
5
XRAS
XWE
2
4
XWE
XCAS
XCAS
9
23
LRMU
61
LRMU
A
AOUT1
51
CD-L
(Page 17)
LPF
AOUT2
2
56
R-CH
XTAI
47
X601
16.934MHz
XTAO
48
TESET
CONNECTOR
CN801
VCPU
RESET
B
(Page 17)
30
78
21
22 23
16
16
IC702
SOUND PROCESSOR
DAC
INTERFACE
CD-ROM
INTERFACE
8
INTERRUPT CONTROLLER
MAGIC GATE
CORE
DMAC(CH3)
DMAC(CH1)
DMAC(CH2)
DMAC(CH0)
RAM
160K BYTES
WATCHDOG TIMER
CLOCK GENERATOR/
SYSTEM CONTROLLER
PRESCALLER/
TIME BASE TIMER
RAM
512K BYTES
HUFFMAN HW
VIRTUAL ENGINE
IC802
EEPROM
DO
4
3
DI
XSK
2
XCS
1
67
18
19
20 17
60
66
11
RF3/T3
37
SCS0
42
SIO
41
SO0
40
SCK0
38
RF0
34
X701
22MHz
EXTAL
29
XTAL
30
CORE
33
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