Current Protection: Negative Phase Sequence Overcurrent - (46Nps); Figure 3-17 Logic Diagram: Cold Load Settings (51C) - Siemens 7SR10 Argus Series Manual

CB Open
CB Closed
&
Open
&
Closed
Reduced
Reduced
Current Level
Current
c
Enabled
Disabled
<
IL1
<
IL2
<
IL3
3.4.6

Current Protection: Negative Phase Sequence Overcurrent - (46NPS)

The negative sequence phase (NPS) component of current (I2) is derived from the three phase currents. It is a
measure of the quantity of unbalanced current in the system.
When the device is applied to reverse sequence networks, i.e. 1-3-2, the NPS/PPS sequence is corrected
automatically by the Gn Phase Rotation setting in the CT/VT Config menu.
Two NPS current elements are provided – 46IT and 46DT.
The 46IT element can be configured to be either definite time lag (DTL) or inverse definite minimum time (IDMT),
46IT Setting sets the pick-up current level for the element.
A number of shaped characteristics are provided. An inverse definite minimum time (IDMT) characteristic is
selected from IEC and ANSI curves using 46IT Char. A time multiplier is applied to the characteristic curves using
the 46IT Time Mult setting. Alternatively, a definite time lag delay (DTL) can be chosen using 46ITChar. When
Definite Time Lag (DTL) is selected the time multiplier is not applied and the 46IT Delay (DTL) setting is used
instead.
The 46IT Reset setting can apply a definite time delayed or ANSI (DECAYING) reset.
The 46DT element has a DTL characteristic. 46DT Setting sets the pick-up current and 46DT Delay the follower
time delay.
Operation of the negative phase sequence overcurrent elements can be inhibited from:
Inhibit 46IT
Inhibit 46DT
©2018 Siemens Protection Devices Limited
Cold Load
Enabled
Disabled
Inhibit Cold Load
Pick- up Time
CB
Drop- off Time
CB
Reduced Current DTL
&

Figure 3-17 Logic Diagram: Cold Load Settings (51c)

A binary or virtual input.
A binary or virtual input.
&
S
Q
≥1
51c- n Setting
R
51c- n Charact
51c- n Time Mult
51c- n Delay ( DTL)
51c- n Min . Operate T ime
51c- n Follower D TL
51c- n Reset
c
c
L 1 Dir En
c
L 2 Dir En
c
L 3 Dir En
7SR10 Description of Operation
51c
See Delayed
Overcurrent
(51-n)
P ic kup
≥1
General Pickup
t ri p
P ic kup
t ri p
P ic kup
≥1
51-n
t ri p
Chapter 1 Page 41 of 77