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AC75 Hardware Interface Description
Strictly confidential / Preliminary
3.15.4.2
Slave Mode
In slave mode the PCM interface is controlled by the external bit clock and the external frame
sync signal applied to the pins BCLKIN and FSIN. If the short frame format is selected, the
data transfer starts with the falling edge of FSIN, otherwise the rising edge is used. With this
edge control the frame sync signal is independent of the frame sync pulse length.
The bit clock frequency has to be in the range of 256kHz -125ppm to 512kHz +125ppm.
TXDAI data is shifted out at the rising edge of BCLKIN. Data transmitted to RXDAI from the
external application is sampled at the falling edge of BCLKIN.
The deviation of the external frame rate from the internal frame rate must not exceed
±125ppm. The internal frame rate of nominal 8kHz is synchronized to the GSM network.
The difference between the internal and the external frame rate is equalized by doubling or
skipping samples. This happens for example every second, if the difference is 125ppm.
The resulting distortion can be neglected in speech signals.
The pins BITCLK and FS remain low in slave mode.
Figure 31 shows the typical slave configuration. The external codec delivers the bit clock and
the frame sync signal. If the codec itself is not able to run in master mode as for example the
MC145483, a third party has to generate the clock and the frame sync signal.
The following figures show the slave short and long frame timings. Because these are edge
controlled, frame sync signals may deviate from the ideally form as shown with the dotted
lines.
AC75_HD_V00.202
AC75
BCLKIN
FSIN
TXDAI
RXDAI
Figure 31: Slave PCM interface application
Page 72 of 120
s
bitclk
Frame Sync
RX_data
TX_data
CODEC
27.04.2006
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